成果報告書詳細
管理番号20100000001164
タイトル*平成21年度中間年報 極低電力回路・システム技術開発(グリーンITプロジェクト)
公開日2010/10/26
報告書年度2009 - 2009
委託先名株式会社半導体理工学研究センター 国立大学法人東京大学 学校法人慶應義塾
プロジェクト番号P09003
部署名電子・情報技術開発部
和文要約和文要約等以下本編抜粋:1. 研究開発の内容及び成果等
[1] ロジック回路技術開発
ロジック回路部の消費電力は電源電圧に大きく依存するため、電源電圧を極限まで低減した「極低電圧(0.5V以下)動作のロジック回路技術」の研究開発を進めている。極低電圧ではばらつきの影響が増加し、これまでロジック技術領域ではそれほど問題視されていなかったランダムばらつきへの対策も必要になる。平成21年度は、極低電圧でのロジック回路動作課題を抽出する評価技術を中心に開発し、課題を解決する候補技術については要素回路の基本検討を行った。
英文要約Title: Extremely Low-Power Circuits and Systems Technology Development Project (Green IT project) (FY2009-2010) FY2009 Annual Report
1. Extremely low voltage logic circuits: Circuit simulation and 65nm TEG measurement results confirmed that VDDmin is one of the most important parameters under extremely low voltage operation. Matrix array TEGs for estimation of device variation influence, 16-bit integer unit TEGs for getting reference data of power consumption and error rate, and fine grained adaptive control TEGs of pipeline timing and redundant circuit components for improvement of extremely low voltage circuit characteristics, have been developed using 65nm CMOS process technology.
2. Memory circuits for extremely low power consumption: 2.1 Advanced assist circuits for low voltage and low power SRAM operation: Advanced assist circuits with bit line power reduction control has been developed. The circuits enable to reduce power consumption of SRAM macro to less than half. 2.2 Novel memory cell technology and related low power peripheral circuits: Three times faster operation speed has been confirmed with newly developed 8-transistor cell on very low voltage condition. 2.3 Circuit techniques to decrease transistor local variation by applying electrical stress: Static noise margin enhancement by self-convergence technique has been proved with fabricated SRAM chip.
3. Extremely low-power analog circuits: A system model of a digital rich phase-locked loop (PLL) has been developed and the target specification of clock jitter (less than 1%) and lock time (less than several tens of reference clock cycles) has been confirmed by the system level simulation. Building blocks of PLL, such as digitally-controlled oscillator, have been designed and circuit simulation achieves the required frequency range and the phase noise. The test chip implemented in 65nm-CMOS process verified the wide frequency range and low-voltage operation. A 0.5V extremely low-power analog-to-digital converter has been designed which includes the bootstrap circuit and split-capacitor DAC for the reduction of power consumption. Power reduction of more than two orders magnitude has been confirmed by the circuit simulation.
4. Power management and conversion circuits: The purpose of this research project is to achieve low power VLSI’s with the 0.5-V power supply voltage by developing a new power management circuits with the 0.5-V output voltage and a new adaptive power management system with logic circuits. In FY 2009, conventional power management circuits including DC-DC converters, linear regulators, and charge pumps are designed and fabricated, and the problems in designing the 0.5-V power management circuits are clarified.
5. Extremely low power wireless communication circuits: 5-A. Ultrahigh-speed peer-to-peer wireless communication: In the project of ultrahigh-speed peer-to-peer wireless communication, communication speed more than 10 giga bit per second will be realized of short-millimeter-wave CMOS circuits with the power efficiency of 50pJ/bit. In FY 2009, the following research development was performed. For the design of short-millimeter-wave circuits, optimization of physical layout as well as circuit topology is required. For the optimization, device models were established with the fabrication of test element groups (TEGs). To realize extremely low power of 50pJ/bit in short-millimeter-wave wireless communication, optimum architecture based on millimeter-wave pulse communication system was discussed, and block diagram of the transceiver is established, where power consumption and level diagram were estimated.
ダウンロード成果報告書データベース(ユーザ登録必須)から、ダウンロードしてください。

▲トップに戻る