成果報告書詳細
管理番号20100000001165
タイトル*平成21年度中間年報 極低電力回路・システム技術開発(グリーンITプロジェクト) アナログ回路技術開発
公開日2010/10/26
報告書年度2009 - 2009
委託先名システムエルエスアイ株式会社 国立大学法人東京工業大学
プロジェクト番号P09003
部署名電子・情報技術開発部
和文要約和文要約等以下本編抜粋:1. 研究開発の内容及び成果等
(1)極低電力PLL 低電圧におけるクロックジッタ特性劣化の原因解明と対策回路の検討文献のアーキテクチャを検討した。また、MATLABシミュレーションを用いてMR-PLLの性能とフィルタ特性を評価した。
英文要約Title: Ultra-low voltage circuits and system development for Green IT Project with analog circuit technique (FY2009-FY2010)FY2009 Annual Report
(1)PLL: Several architectures were reviewed and discussed to meet the specifications with emphasis on power consumption. We conclude that analog PLL circuits should use a fully differential scheme as much as possible to minimize noise interferences and to maximize the signal dynamic range. A multi sampling rate PLL has been selected for our top level architecture to meet the design goals. Several digital circuits have been designed to support the implementation and many dynamic logic circuits have been used to meet the speed requirements. Some of layout designs using 90nm CMOS have been started.
(2)ADC: In order to achieve high speed operation with 0.5V power supply, a comparator with forward biased MOS FETs was investigated. With this forward biased MOS FETs, the comparator showed a 66% reduction in response delay over non forward biased one. Furthermore, a double tail latch circuit shows higher performance at 0.5V operation. Using this technique, a 5 bit parallel ADC has been designed in 90nm CMOS technology. The simulation results suggest that this ADC will consume a half of the smallest power ever reported with conversion speed of 500MHz.
(3)DAC: To meet the 0.5V operation, we optimized the bias circuit and developed thecurrent control circuit without conventional OpAmps. This new DAC has been designed and laid out using 90nm CMOS. The simulation results suggest that this DAC consume one fifth of the smallest power ever reported.
(4)VCO: To meet the requirement for 0.5V and low power operation, LC type VCO was chosen. Theoretically LC VCOs consume one thousandth power of those of ring OSCs however have drawbacks of instable operation and narrow tuning range under low voltage power supply. In this design a bias tuning circuit was employed to cope with the instability and a set of programmable dividers were utilized to extend its tuning range. This new VCO has been designed and laid out using 90nm CMOS. The simulation results show that this VCO consumes 0.7mW to 0.9mW outputting 50MHzto 3GHz clocks. FOM number of -181dBc/Hz which shows an extremely low phase noise characteristics has been realized.
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