成果報告書詳細
管理番号20110000000711
タイトル*平成22年度中間年報 省エネルギー革新技術開発事業 先導研究 省エネ情報機器のための超並列バスによるヘテロジニアス・マルチチップ積層 Cool System の研究開発(1)
公開日2011/6/7
報告書年度2010 - 2010
委託先名株式会社トプスシステムズ
プロジェクト番号P09015
部署名エネルギー対策推進部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等
動作クロック周波数3GHzのCore2Duoプロセッサ(Intel社製)と同等の処理性能を、動作周波数を50MHzに低減することで、消費電力を1/50に削減する超並列バスによるヘテロジニアス・マルチチップ積層Cool Systemの研究開発を進めた。解決すべき課題を図1に示す。
平成22年度末までに、FPGAボードで論理機能評価(10MHz以上)という目標に対し、FPGAボードは目標を上回る50MHzでの動作を確認できたが、ヘテロジニアス・マルチチップの設計が当初予定よりも複雑化しており論理機能評価完了までは至っていない。
また、試作チップで超並列通信バス評価(50MHz以上)という目標に対し、試作チップは完成したが、未だ回路動作の評価中であり、超並列通信バス評価完了までは至っていない。(図2)
英文要約"R&D of Heterogeneous multi-layered-chip Cool System with super-parallel signal bus for energy saving information systems"
Intermediate annual report of FY2010 of FY2009-FY2011
TOPS Systems Corp.
This project aims to reduce the clock frequency of microprocessor without degrading its performance for a drastic power reduction.
To achieve power reduction by 1/50, we overcome three major challenges; 1) Design a microprocessor to be stacked as a 3-D LSI chip without heat issues, 2) Improve processor core utilization with distributed software, 3) Establish a Scalable Low-Power inter-chip connection for 3-D LSI chips.
We have developed a prototyping system that runs at 50MHz which exceeds the goal of 10MHz. The functional evaluation of a heterogeneous Multi-Core/Multi-Chip design using the prototyping system is underway. A test chip of Inter-Chip connection was fabricated, and the circuit level evaluation is also currently underway.
R&D Item 1, "Cool Chip Technology"
1) Development of a heterogeneous multi-chip processor system
- Developed a Heterogeneous Multi-Chip/Multi-Core architecture for a next generation digital-TV platform that can achieve high performance comparable to a 3GHz Core2Duo processor. It consists of 4 chips stacked as 3-D LSI with 9 heterogeneous Multi-Cores with two of them running at 50MHz.
- The microprocessor chips size are estimated to be more than 10 times smaller than a Core2Duo when using a same technology (58mm2 in TSMC 0.15um).
2) Performance evaluation of the heterogeneous multi-chip system using FPGA boards
- Developed a prototyping system for 3-D LSI systems
We solved a prevalent issue of 3-D LSI’s prototyping systems; such is the number of interconnections, with a stackable FPGA based board design. We also enabled “Real-Time System Performance Evaluation” by designing it to run at 50MHz which is the same frequency as the target chip.
R&D Item 2, "Cool Software Technology"
1) Implementation and evaluation of image processing software
- Designed application specific complex instructions that effectively reduce the clock frequency required for next generation digital-TV applications. The design continues until all application requirements are covered.
- 65.2% utilization of heterogeneous Multi-Cores was achieved with a stream processing H.264 decoder. This surpassed the goal of 60% of utilization.
- 65% of Core2Duo’s performance was achieved with a stream processing JPEG decoder.
2) Evaluation of the super-parallel communication bus.
- Developed a bus called “COOL Interconnect” which consists of a logic layer, a circuit layer, and a physical layer. It provides scalability in number and type of connecting chips and 6.4GB/s bandwidth that is high enough for next generation digital-TV applications that requires 500MByte/s in the case of using 16 cores for processing.
- Developed a test chip of COOL Interconnect for power and performance evaluation. The physical interconnect area integrating 1600TSVs is 2mm by 2mm, which is comparable to I/O pad ring area of conventional LSI chips.
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