成果報告書詳細
管理番号20110000001313
タイトル*平成22年度中間年報 次世代高効率ネットワークデバイス技術開発(1)
公開日2011/11/26
報告書年度2010 - 2010
委託先名財団法人国際超電導産業技術研究センター
プロジェクト番号P07012
部署名電子・材料・ナノテクノロジー部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等 1) SFQ回路を用いた光ネットワーク技術開発に用いる超電導回路の開発 超電導リアルタイムオシロスコープの中核部品となる超電導ADコンバータ(ADC)の開発を行った。H21年度までに新方式の相補型コンパレータと、コンパレータ遷移領域の動作不安定性を補償するエラー補正回路からなるADCの動作に成功し、最高34GS/sのサンプリング速度が可能であることを実証できた。H22年度は使用するジョセフソン接合(JJ)の臨界電流密度(Jc)を増加することにより高速化を行った。また、入力とコンパレータ結合部分やエラー補正回路の回路方式を見直し、より高速でより安定した動作実現を目的とした高度化を行った。
JJのトンネルバリア形成条件の最適化を行い、従来比4倍のJc=10kA/cm2のJJを安定して製造できる見通しを得た。また、臨界電流値を一定に保つためにJJ面積を1/4に縮小した。これにより、最小JJ面積は4μm2から1μm2に縮小されたが、ADC回路動作に支障がない程度の臨界電流均一性(JJ面積均一性)を保持できることを確認した。
英文要約High-speed Analog to Digital Converter (ADC) is a key component of a superconductive real-time oscilloscope. We have developed Single-Flux-Quantum (SFQ) ADC with 5-bit accuracy. Critical current density (Jc) of Josephson junctions (JJ) in the circuit was increased to 10 kA/cm2 for improving operation speed. This value is four times larger than that in previous design and junction sizes have to be reduced to one forth for keeping critical current value. Sampling frequency was increased to 50 GS/s from 34 GS/s by increasing the Jc. This value satisfies our final target.
We have also investigated circuit design of the ADC to improve operation stability. Unstable operations which were observed in last year were effectively decreased by optimizing return paths for bias current. Two types of the error correction circuit, such as a clock-flow type and a semi-synchronous type, were tested.
In order to improve input bandwidth to the ADC, resistance value in a resistance ladder and coupling between an output of the ladder and a comparator were reconsidered. Frequency dependency of input current distribution ratio by the ladder was dramatically improved by replacing 20Ω resistance with 20μm width to 50Ωone with 8μm width. This is because the resistance matched impedance to the input line in the comparator. The input bandwidth was increased to 13 GHz for 4 bit (binary) from 7 GHz and 20 GHz for 3 bit (binary) from 15 GHz by using smaller trance in comparator, matching impedance in the ladder output coil and adopting a sandwich structure for the comparator input coil.
ISTEC and Yokohama National University developed a shift register circuit which converts clock speed from the ADC to room temperature electronics. A 64-bit shift register circuit using the 10 kA/cm2 process operated correctly with ±27% bias margin. Operation speed of the circuit was confirmed more than 50 GHz which matched the demand for the speed conversion.
We studied SFQ circuits using higher Jc collaborated with Nagoya University. A divider circuit and shift register circuit were designed, fabricated and tested with Jc=40 kA/cm2. The maximum frequency of the divider was 425 GHz and the shift register had enough operation margins.
ISTEC and NICT improved sensitivity of an optical signal input module from 1530 to 1570 nm wavelength at cryogenic temperature. The module was made by In1-xGaxAs. We made an adjustment the x to 0.44 from 0.47 and could the sensitivity of 0.033 A/W at 1570 nm which was one order higher compared with conventional module.
A Josphson AC voltage standard device and its cooling system were developed by ISTEC and AIST to evaluate the ADC. Mechanical vibration and ground noise were reduced by a pulse-tube cooler and outer conductor insulations of microwave cables.
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