成果報告書詳細
管理番号20110000001316
タイトル*平成22年度中間年報 立体構造新機能集積回路(ドリームチップ)技術開発
公開日2011/11/26
報告書年度2010 - 2010
委託先名技術研究組合超先端電子技術開発機構
プロジェクト番号P08009
部署名電子・材料・ナノテクノロジー部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等 半導体製品の更なる性能向上を図るため、二次元的な微細化に加えて、三次元的なチップ積層構造を採用することにより、高集積化、配線遅延低減、低消費電力化や、開発期間の短縮を実現することが可能になる。すなわち、微細化に伴い、配線抵抗、配線容量の増大に起因する信号遅延時間増大、消費電力増加が顕在化してきているが、配線抵抗の低減には、TSV(Si貫通ビア:Through Si Via)を活用した半導体チップの三次元集積化が有効である。TSVによる三次元的接続法は、超ワイドバス化が可能であり、従来に無い大容量高速の信号伝送を可能にする。さらにこの技術を用いてCMOS 半導体デバイスと他の機能デバイスとの三次元集積化を行えば、従来にない多機能デバイスの実現が可能となる。
英文要約Title: Development of Functionally Innovative Three-dimensional Integrated Circuit (Dream Chip) Technology (FY2009-FY2010) FY2010Annual Report
(Design Environment Technology) The speeding up electrical circuitry simulator to approximately 1,000 times of conventional SPICE, using innovative algorithms, was achieved. The speeding up electromagnetic simulator to more than 500 times of current one through the ADE-FDTD method and the mesh number decreasing method, was achieved. (Interposer Technology) The improvement of SI/PI for high frequency circuits by decoupling-capacitor-embedded interposers were quantitatively evaluated with the developed power noise evaluation system. High efficiency 3D-Integrated DC-DC converter using Si interposer was developed and demonstrated. The SI/PI for high frequency circuits of interposers mounting various types of decoupling capacitor were quantitatively evaluated by developed power noise evaluated system. High efficiency 3D-Integrated DC-DC converter using Si interposer was developed and evaluated.(Chip Test Technology) Using contact and contactless connectors for whole wafers, the 1/10 model of a probe card system that can handle φ300 mm wafers with 150,000 contact connectors and 36,000 contactless connectors was demonstrated. A transmission speed of 1 Gbps was confirmed employing developed ASIC for tester chip and probe chip. (Cooling, Stacking and Bonding Technology) A high-density 3D-integrated structures were evaluated and thermal resistance between bonded bump chips were determined. The 3D stacking and bonding of C2C employing pre-apply resin method with a fine pitch of 10-micron level was developed. (Thin Wafer Technology) The possibility for thinning and handing 10-micron thickness wafer method was demonstrated. Relationship between gettering method and Cu contaminant suppression was revealed. (Demonstration Device and Process) Targeting a high speed image processing system that works at 10,000 frames/sec in VGA for Demonstration Device #2, the evaluation of the element circuit was completed. For Demonstration Device #1 with a 2-chip structure (logic and super-wide bus memory), chips production was completed and evaluation has started. Development of technologies to form and to make via fill plating of a TSV for φ5 μm, and micro-bumps technology was completed. (3D Reconfigurable Device, Architecture) A scalable reconfigurable IO processor was designed. Architecture for FPGA and it’s 3D-SiP containing communication circuit system were designed, then their performance were evaluated. (3D Reconfigurable Devic,3D Integration) Development of element technologies of via last TSV, bump formation and wafer stacking for 3D-integlation was completed. Design rule for the process was formulated. (3D Integrated RF Device for Multi-band Communication System, RF MMES Device & Front End Circuits) New designed MEMS switch increasing the contact point loading force to improve reliability was prototyped and confirmed. Tunable filter with narrow passband method along with center variable frequency function was validated.
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