成果報告書詳細
管理番号20110000001320
タイトル*平成22年度中間年報 極低電力回路・システム技術開発(グリーンITプロジェクト)(1)
公開日2011/11/26
報告書年度2010 - 2010
委託先名株式会社半導体理工学研究センター 国立大学法人東京大学 学校法人慶應義塾
プロジェクト番号P09003
部署名電子・材料・ナノテクノロジー部
和文要約和文要約等以下本編抜粋:1. 研究開発の内容及び成果等 [1] ロジック回路技術開発 ロジック回路部の消費電力は電源電圧に大きく依存するため、電源電圧を極限まで低減した「極低電圧(0.5V 以下)動作のロジック回路技術」の研究開発を進めている。極低電圧ではばらつきの影響が増加し、これまでロジック技術領域ではそれほど問題視されていなかったランダムばらつきへの対策も必要になる。平成22 年度は、前年度に開発した極低電圧でのロジック回路動作課題を抽出する評価TEGと、課題を解決する候補技術の要素回路TEG の測定を進めるとともに、測定結果の解析と新たに判明した課題に対する改善技術の検討や40nm 回路TEG の開発を進めた。提案技術による低電圧化により、16bit整数演算TEG(65nm CMOS)の評価結果から、中間目標である電力3/10 以下を達成した。
英文要約Extremely Low-Power Circuits and Systems Technology Development Project (Green IT project) (FY2009-2010) FY2010 Annual Report
1. Extremely low voltage logic circuits: Measurement results of a 16-bit integer unit TEG, which fabricated in 65 nm CMOS technology, confirmed that VDDmin and 70% power reduction, which is this year’s target, can be achieved by employing proposed extremely low voltage logic circuit technologies. For improvement in the circuit characteristics, new circuit technology TEGs have been developed using 40nm CMOS technology.
2. Memory circuits for extremely low power consumption: 2.1 Advanced assist circuits for low voltage and low power SRAM operation: SRAM macro with the newly proposed bit line power reduction control circuits has been fabricated. The fabricated SRAM macro shows the smallest active power consumption compared to the previous works ever reported. 2.2.1 Novel memory cell technology and related low power peripheral circuits: The fabricated SRAM macro with newly developed 8-transistor cell has achieved more than ten times faster operation speed at 0.5V compared to the previous works. 2.2.2 Circuit techniques to decrease transistor local variation by applying electrical stress: Static noise margin enhancement without sacrificing write margin by injecting hot carriers into the access transistors has been proved with fabricated SRAM memory cells.
3. Extremely low-power analog circuits: A digitally-controlled oscillator (DCO) and a time-to-digital converter (TDC) have been designed as the building blocks of PLL. The DCO implemented in 40nm-CMOS process achieved the power consumption of 0.3uW/MHz and cycle-to-cycle jitter of lower than 0.3%. The fabricated TDC adopted pipeline architecture has resolution scalability and achieved 10bit resolution. Successive-approximation-register type analog-to-digital converter (SAR-ADC) has been designed using 40nm-CMOS process. The fabricated ADC operates 1.1uW/MHz with an effective resolution of 7.5bit. 4. Power management and conversion circuits: The purpose of this research project is to achieve low power VLSI’s with the 0.5-V power supply voltage by developing a new power management circuits with the 0.5-V output voltage and a new adaptive power management system with logic circuits. In FY 2010, several new 0.5-V power management circuits are proposed and verified through LSI measurements.5-A. Ultrahigh-speed peer-to-peer wireless communication: In the project of ultrahigh-speed peer-to-peer wireless communication, communication speed more than 10 giga bit per second will be realized of short-millimeter-wave CMOS circuits with the power efficiency of 50pJ/bit. In FY 2010, the following research development was performed. For the design of short-millimeter-wave circuits, optimization of physical layout as well as circuit topology is required. For the optimization, device models established in FY 2009 were verified with the measured results of a low-noise amplifier. To realize extremely low power of 50pJ/bit in short-millimeter-wave wireless communication, optimum architecture based on millimeter-wave pulse communication system was discussed, and architecture of the transceiver was verified by fabrication of a 120GHz CMOS transceiver chip with loop-back test. Finally, initial wireless communication was performed in 120GHz band using a fabricated CMOS receiver with 28.7pJ/bit (3Gbps/86mW).
5-B. Chip-to-chip non-contact interfaces: In the development of the non-contact interfaces, pulse transmitter and receiver amplifier has been designed and fabricated in 65nm-CMOS process. The transmitter contains pulse boot-strapping circuit and can generate current pulse signals with a rate of 1.1Gbps.
ダウンロード成果報告書データベース(ユーザ登録必須)から、ダウンロードしてください。

▲トップに戻る