成果報告書詳細
管理番号20110000001321
タイトル*平成22年度中間年報 極低電力回路・システム技術開発(グリーンITプロジェクト) アナログ回路技術開発
公開日2011/11/26
報告書年度2010 - 2010
委託先名国立大学法人東京工業大学 システムエルエスアイ株式会社
プロジェクト番号P09003
部署名電子・材料・ナノテクノロジー部
和文要約和文要約等以下本編抜粋:1. 研究開発の内容及び成果等 (1)極低電力PLL PLL基礎機能評価用TEGチップの性能評価 チップ全体のレイアウト設計後、負荷容量等のパラメータを利用したシミュレーションを行なった。TSMC90nm CMOSプロセスで50個のTEGチップを作成後、TEGチップの評価基板開発を行いPLL基礎機能評価用TEGチップの基本動作確認と特性評価を行なった。以下の評価結果の通り、各項目の最終目標値に対して10MHz時の消費電力と800MHz時の20kHz位相雑音以外は最終目標値を達成した。実証機能評価TEGチップで改善を図った。
英文要約Title: Ultra-low voltage circuits and system development for Green IT Project with analog circuit technique (FY2009-FY2011)FY2010 Annual Report
 (1)PLL: Several architectures were reviewed and discussed to meet the specifications with emphasis on power consumption. We conclude that analog PLL circuits should use a fully differential scheme as much as possible to minimize noise interferences and to maximize the signal dynamic range. A multi sampling rate PLL has been selected for our top level architecture to meet the design goals. Several digital circuits have been designed to support the implementation and many dynamic logic circuits have been used to meet the speed requirements. Some of layout designs using 90nm CMOS have been started. The first and second passes of the PLL hardware in TSMC 90nm CMOS have been designed,fabricated and evaluated. Clock jitters were 0.5% at 10MHz, and 0.9% at 100MHz. Power consumptions were 10uW at 10MHz, and 60uW at 100MHz. Phase noises were -91dBc at 1kHz offset, and -101dBc at 20kHz offset. The PLL was powered by a single 0.5V. Started evaluation of TSMC 65nm(40nm logic node equivalent) technology and its performance seemed to be equivalent to that of 90nm.  (2)ADC: In order to achieve high speed operation with 0.5V power supply, a comparator with forward biased MOSFETs was investigated. With this forward biased MOSFETs, the comparator shows a 66% reduction in delay time as compared with that without the forward biase. Furthermore, a double tail latch circuit shows higher performance at 0.5V operation. Using this technique, a 5-bit parallel ADC has been designed in 90nm CMOS technology. The measured results show that the proposed ADC can perform 5-bit 600Ms/s conversion with a 1.2-mW power consumption. (3)DAC: To meet the 0.5V operation, we have developed a bias current control circuit without the conventional OpAmps. This new DAC has been designed and was fabricated by a 90nm CMOS process. The measurement result shows that this DAC consume one tenth of the smallest power ever reported, which is only 1.4mW. (4)VCO: To meet the requirement for 0.5V and low power operation, CMOS-LC type VCO was chosen. Theoretically LC VCOs consume one thousandth power of those of ring oscillators, however, have drawbacks of narrow tuning range under low voltage power supply. In this design, a set of programmable dividers are used to extend its tuning range. This new VCO has been designed and was fabricated by a 90nm CMOS process. The measured results show that this VCO consumes 0.9mW including 0.3mW core VCO power, which can output 50MHz to 6GHz clocks. A phase noise of -109dBc/Hz-1MHz has been realized at 3GHz.
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