成果報告書詳細
管理番号20110000001374
タイトル*平成22年度中間年報 ナノエレクトロニクス半導体新材料・新構造ナノ電子デバイス技術開発 シリコンナノワイヤトランジスタの物性探究と集積化の研究開発
公開日2011/12/13
報告書年度2010 - 2010
委託先名国立大学法人東京大学生産技術研究所 株式会社東芝
プロジェクト番号P09002
部署名電子・材料・ナノテクノロジー部
和文要約和文要約等以下本編抜粋:1. 研究開発の内容及び成果等 (1)極細シリコンナノワイヤトランジスタの電気伝導探究と集積化に関する研究開発(国立大学法人東京大学) (i) デバイス作製 前年度に確立したワイヤ径5nmから15nm程度の極めて細いナノワイヤトランジスタ作製技術をさらに発展させて,ナノワイヤ幅とナノワイヤ高さを変化させてナノワイヤトランジスタアレーを作製した。シリコンナノワイヤトランジスタの寄生成分の影響を除外して正確に移動度を評価するために,ナノワイヤ長さのみが異なる複数のトランジスタを作製した.
英文要約Development of Nanoelectronic Device Technology (FY2010) FY2010 Annual Report
1-(3) Si nanowire transistor
University of Tokyo and Toshiba Corporation
(1) Research and development on electric transport and integration of long channel ultra-narrow silicon nanowire transistors (University of Tokyo)
In order to develop the design guideline for high mobility silicon nanowire transistors, strain is applied to the fabricated nanowire transistors and the effect of strain on electric characteristics is intensively investigated. It is found that narrower n-type nanowire transistors show higher improvement of drain current by strain, while wider p-type nanowire transistors show higher improvement of drain current by strain. Combined with the nanowire width dependence of electron and hole mobility, it is clarified that the optimum nanowire width of nanowire transistor is approximately 9nm.
(2) Research and development on electric transport and integration of short channel silicon nanowire transistors (Toshiba Corporation)
We successfully fabricated tri-gate type silicon nanowire transistors with 15-nm-nanowire-width and 15-nm-gate-length on 300-mm diameter (100) SOI wafers. We successfully reduced the parasitic resistance of Si nanowire transistors by raised source/drain with ultra-thin gate side-wall spacer less than 10 nm. The ultra-thin gate side-wall spacer increased Ion by 140% in n-MOSFETs compared with the conventional gate side-wall spacer of 30 nm. We systematically studied short-channel mobility in nanowire transistors. The strain induced in the NW channel dominates short-channel mobility. The mobility of short-channel nanowire nMOSFETs largely increases due to vertical compressive strain. We achieved further strain enhancement by stress memorization technique (SMT). The mobility increase by SMT is much larger in nanowire transistor than in planar transistor In <110> NW nFETs, the on-current on the same DIBL largely increases by SMT thanks to significant reduction of parasitic resistance in addition to the mobility enhancement.
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