成果報告書詳細
管理番号20110000001376
タイトル*平成22年度中間年報 ナノエレクトロニクス半導体新材料・新構造ナノ電子デバイス技術開発2
公開日2011/12/13
報告書年度2010 - 2010
委託先名独立行政法人産業技術総合研究所 株式会社東芝
プロジェクト番号P09002
部署名電子・材料・ナノテクノロジー部
和文要約和文要約等以下本編抜粋:1. 研究開発の内容及び成果等 ゲート長がサブ10 nm の領域に到達すると、ゲートのチャネルに対する制御能力を最大化するために、直径がnm レベルのナノワイヤ構造をチャネルに採用することが必須になる。この領域
では、量子効果が顕在化し、その利点を活かして高い性能を実現することが期待できる一方、原子レベルの構造揺らぎもデバイス特性に顕著な影響を与え、特性バラツキが今以上に深刻な課題になることが懸念される。
本研究開発では、量子効果が顕在化する特性寸法が10nm 以下のナノワイヤトランジスタを対象に、高精度なデバイス試作と電気的特性評価、物理計測評価解析、デバイスシミュレーションを含む計算科学的解析を、総合的に行う。これによって、CMOS の究極形としてのナノワイヤトランジスタの特性を予測し、構造・材料・プロセスの設計を行うための基盤的知識体系を、科学的な裏付けを持って構築することを目的としている。
英文要約Title: Development of Nanoelectronic Device Technology Project, Comprehensive Study of Si Nanowire Transistors and Related Technologies (FY2009-FY2011) FY2010 Annual Report
The objective is to develop a comprehensive technology of Si nanowire (SNW) transistors ranging from precise fabrication processes to related measurement and characterization techniques and simulation methods. We have developed an etching technique for SNW fabrication using active oxidation of Si surfaces. This technique reduced the width and line edge roughness of SNW and enabled us to fabricate ultrathin SNW FETs with a HfO2 gate stack and NiSi2 source/drain. Clear on/off operation was confirmed for the SNW FET with 8 nm diameter. As a measurement technique of SNWs, the ability of x-ray scattering was shown for analyses of shape and internal structure of periodically-arranged SNWs of about 30 nm in diameter. In order to realize atomic force microscope (AFM) metrology for three-dimensional structure, we have developed a scanning technique of a tilted tip with the tilted direction of force tracking control, while the traditional AFM tracks the atomic force along the vertical direction. AFM images of vertical or undercut sidewalls have been successfully taken. To measure the potential distribution with nm resolution on an electrically isolated SNW, metal-tip needle-sensor probes were fabricated by the focused ion beam technique and utilized for simultaneous measurements of tunneling current and contact potential difference (CPD) distributions in 20-nm-wide SNWs. Several simulation techniques are under development over multi-scale formulations ranging from ab-initio calculation to device simulator. For example, we have investigated the Schottky barrier height of the NiSi2/Si(111) interface and the current-voltage characteristics of SNW sandwiched by NiSi2 electrodes using first principle calculations. It was shown that the barrier height for p-type SNW is reduced to 0.1 eV by the segregation of B atoms at the Si side of the interface. The device characteristics of SNW FETs and double-gate MOSFETs have been evaluated using the developed Monte Carlo simulator, in which the long-range Coulombic interaction is exactly incorporated. We have found that electron transport in SNW FETs becomes more diffusive due to scattering in the confined channel, compared to that in double-gate MOSFETs.
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