成果報告書詳細
管理番号20110000001377
タイトル*平成22年度中間年報 ナノエレクトロニクス半導体新材料・新構造ナノ電子デバイス技術開発 シリコンプラットフォーム上3~5族半導体チャネルトランジスタ技術の研究開発
公開日2011/12/13
報告書年度2010 - 2010
委託先名独立行政法人産業技術総合研究所 国立大学法人東京大学 独立行政法人物質・材料研究機構
プロジェクト番号P09002
部署名電子・材料・ナノテクノロジー部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等 (1)研究開発の内容
電子の有効質量が小さく移動度が大きいIII-V族半導体を用いたMISFETは、hp22nm以細のCMOSにおける性能向上や低消費電力化を可能にするデバイスとして期待されている。このデバイスが適用される技術世代においては、高い電流駆動力を持ち、かつ、短チャネル効果抑制にも優れたMISFETを、絶縁膜の上に薄膜III-V族化合物半導体を形成したIII-V-On-Insulator (III-V-OI)構造を用いてSiプラットフォーム上にて実現することが求められる。
本研究は、Si基板上更にその上の絶縁膜上に形成したIII-V族半導体をチャネルとするMISFETを開発するために、最適素子構造・材料の明確化を進め、本デバイスの当該世代CMOSへの適用性を明らかにすると共に、集積化可能性を検証することを最終目標として研究開発を進めている。
英文要約Title: Development of Nanoelectronic Device Technology, Development of Transistor Technology Incorporating III-V Semiconductor Channels on Si Platform (FY2009-FY2011) FY2010 Annual Report
In this study, we are developing MISFETs using III-V channels on Si substrates or insulating layers on Si. In order to realize this device, we have performed the following researches. As for the epitaxial growth of III-V channels on Si, we optimized the pre-treatment process by using P and the condition of initial InAs growth, leading to much improved uniformity of the shape of the InGaAs islands. As for the III-V-OI fabrication by wafer bonding, we optimized the initial substrate structures and the bonding condition, resulting in the InGaAs/Al2O3/Si structures with the InGaAs and Al2O3 thicknesses of 3.2 and 7.7 nm, respectively. The InGaAs-OI layer had the surface roughness and chemical composition comparable to those for the bulk InGaAs wafer. Bonding-induced strain in the InGaAs-OI layer was below the detection limit of Raman spectroscopy. We combined ALD Al2O3 deposition with nitridation of InGaAs surfaces. The MOS interfaces with the nitrided layers exhibited the minimum Dit of 2E11 cm-2eV-1 and the much lower Dit than the MOS interfaces with S treatment. The conductance and the Terman method revealed that that Al2O3/InP interfaces include a large number of slow traps near the conduction band edge of InP. Contribution of the minority carrier responses in the Dit estimation were clarified by analyzing the low-temperature conductance. In-line Auger analyses of the initial growth of Al2O3 on InGaAs revealed that excessive supply of the Al source is effective for obtaining good MIS properties. To realize high-quality interface between the high-k dielectrics and III-V channels, we prepared atomically-controlled Ga-, In-, Al-, and As-stabilized surfaces on InGaAs, and identified their atomic structures. The MOS capacitors fabricated on InGaAs surfaces terminated with higher-atomic-number cation showed lower Dit. It was demonstrated that MISFETs incorporating the InP/InGaAs buried channel show high peak mobility (5,500 cm2/V~s). We developed a fabrication process of self-aligned metal S/D MOSFETs using metallic Ni-InGaAs. It has been found that the Schottky barrier height was reduced with increasing the In content of the InGaAs channels down to zero. We demonstrated the operation of the metal S/D InGaAs MOSFETs with the low S/D resistance and high mobility. The gate-last metal source/drain MISFET process was established for the gate-length scaling as well as for the damage-free assessment of the III-V channels. We demonstrated 9-nm-thick InGaAs-OI nMOSFETs with the peak mobility of 913 cm2/Vs. 3.5-nm-thick nInGaAs-OI MOSFETs under the double-gate operation provided the improved cut-off properties with Ion/Ioff ratio of 1E7. Carrier scattering by the interface dipoles was proposed as the dominant factor limiting the channel mobility in the III-V MISFETs.
ダウンロード成果報告書データベース(ユーザ登録必須)から、ダウンロードしてください。

▲トップに戻る