成果報告書詳細
管理番号20110000001690
タイトル*平成22年度中間年報 「省エネルギー革新技術開発事業/先導研究/強誘電体フラッシュメモリ基盤技術の研究開発」
公開日2012/2/17
報告書年度2010 - 2010
委託先名独立行政法人産業技術総合研究所 国立大学法人東京大学
プロジェクト番号P09015
部署名省エネルギー部
和文要約和文要約等以下本編抜粋:1. 研究開発の内容及び成果等 本研究開発の目的は、低消費電力型の次世代半導体不揮発メモリ素子である強誘電体ゲート電界効果トランジスタ(FeFET)をメモリセルに用いたNAND フラッシュメモリ(Fe-NAND フラッシュメモリ)の実用化のための基盤技術を開発することである。Fe-NAND 研究開発に企業が本格参入するためには、ゲート長(L)が100nm を切る微細化に対応できる要素技術の開発が必要である。従って本研究開発ではFeFET 微細化プロセス研究に特に重点を置き、本研究開発で得られた技術の延長により将来100nm を切る微細化が可能であるようなプロセス要素技術を開発する。本研究開発では、Fe-NAND の100nm を切る技術世代に直結するFeFET 微細化プロセス技術を開発すると当時にFe-NAND フラッシュメモリアレイの動作実証を行うことを最終目標としている。これを達成するため、平成21年度~平成23年度で以下の5項目の研究開発を行う。
(1) FeFET 微細化プロセス技術( 独立行政法人産業技術総合研究所(産総研))
(2) Fe-NAND メモリアレイの作製と評価( 産総研 )
(3) Fe-NAND メモリアレイ評価法開発( 産総研、共同実施先:株式会社東芝(東芝) )
(4) Fe-NAND 制御回路の開発( 国立大学法人東京大学(東大)と産総研 )
(5) Fe-NAND 実用化のためのフィージビリティ研究( 産総研と東大、共同実施先:東芝 )
英文要約Title: Research of basic technology for developing novel ferroelectric flash memory (FY2009-FY2011)
FY2010 Annual Report
This project has five items as follows: (1) Fabrication process for downsizing FeFET, (2) fabrication and statistical evaluation of Fe-NAND flash-memory cell array, (3) Development of test method for Fe-NAND flash-memory cell array, (4) Development of control circuits for Fe-NAND flash-memory, and (5) Feasibility study for commercializing Fe-NAND flash-memory. Summary: This year the target of (1) was to fabricate a self-align gate FeFET which had 200nm-thick ferroelectric layer, less gate length (L) than 1um, larger memory window than 0.85V, larger side-wall angle than 81 degrees, and good retentions at room temperature (RT) by at least 2-day-long measurements. We succeeded to prepare Pt/SBT/HAO/Si FeFETs which completed the all requirements. Using electron-beam lithography, SiO2 hard mask, and high-density plasma etching with a well-optimized condition led to L=0.54um and 85-degree side-wall angle after etched. Self-align source and drain regions were formed by ion-implantation over the gate stacks. The FeFET was covered with SiO2 for device-isolation and sidewall-protection. The FeFETs showed memory windows of 0.95V at Vg=1+/-5V and good retentions at RT by 2-day-long measurements. The target of (2) was to fabricate a Fe-NAND flash memory cell array by non-self-align-gate FeFETs with L=1um. A single cell must have 1E+08 endurance cycles, erase-and-program by 6V 10us pulses, and good retentions at RT by 2-day-long measurements. We fabricated an L=1um 64kb Fe-NAND cell array. The single cell showed 1E+08 endurance cycles, erase-and-program by 6V 10us pulses, and good retentions at RT by 2-day-long measurements. The target of (3) was to develop an accelerated test model by stresses of heating or electric field for the Fe-NAND. We succeeded to find an Arrhenius-type formula to predict a life-time of an FeFET by sampling many FeFETs and analyzed their retention data. The target of (4) was to develop a verify circuit for Fe-NAND cells to control their threshold-voltage (Vth) distribution within 1.5V. A negative word-line voltage step-down erase pulse scheme was proposed. It will accelerate the erase pulse width from 1ms of the conventional well erase to 2us. A 200us/page erase will be realized. The every measured Vth shift was equal to 1/6 of the applied erase-voltage increase. By combining the proposed scheme with the bit-by-bit verify, a 0.07V erase Vth distribution was achieved when the applied erase-voltage increase was 0.4V. The target of (5) was to discuss current problems of Fe-NAND flash memory and to guide the project to output applicable to future commercialized memory. The subjects were mainly about 64kb Fe-NAND memory-array performance this year which gave fruitful feedback and progress to our project. In conclusion, we accomplished all the targets of the project items (1)-(5) in FY2010.
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