成果報告書詳細
管理番号20100000001248
タイトル*平成21年度中間年報 ナノエレクトロニクス半導体新材料・新構造ナノ電子デバイス技術開発 シリコンナノワイヤトランジスタの知識統合研究開発
公開日2012/3/13
報告書年度2009 - 2009
委託先名独立行政法人産業技術総合研究所 株式会社東芝
プロジェクト番号P09002
部署名電子・情報技術開発部
和文要約和文要約等以下本編抜粋:1. 研究開発の内容及び成果等
ゲート長がサブ10 nm の領域に到達すると、ゲートのチャネルに対する制御能力を最大化するために、直径がnm レベルのナノワイヤ構造をチャネルに採用することが必須になる。この領域では、量子効果が顕在化し、その利点を活かして高い性能を実現することが期待できる一方、原子レベルの構造揺らぎもデバイス特性に顕著な影響を与え、特性バラツキが今以上に深刻な課題になることが懸念される。
本研究開発では、量子効果が顕在化する特性寸法が10nm 以下のナノワイヤトランジスタを対象に、高精度なデバイス試作と電気的特性評価、物理計測評価解析、デバイスシミュレーションを含む計算科学的解析を、総合的に行う。これによって、CMOS の究極形としてのナノワイヤトランジスタの特性を予測し、構造・材料・プロセスの設計を行うための基盤的知識体系を、科学的な裏付けを持って構築することを目的としている。
英文要約Title: Development of Nanoelectronic Device Technology Project, Comprehensive Study of Si Nanowire Transistors and Related Technologies (FY2009-FY2010) FY2009 Annual Report
To utilize the nanowire (NW) transistor in actual production, complete understandings of its properties are required together with development of related measurement and characterization techniques and simulation methods. We have developed the etching technique of Si surfaces by annealing in low-pressure oxygen ambient, enabling us to fabricate 4-nm wide Si NW with atomically flat surfaces starting with a 30-nm wide NW fabricated on an SOI wafer with electron beam lithography. This etching process has the advantage that the line edge roughness is also reduced. Si NW transistors were actually fabricated by adopting epitaxial NiSi2 metal source/drains with segregation technique of implanted impurities. Good performances were obtained in both n- and p-channel NW transistors; e.g., the on/off ratio was more than 6 decades with a subthreshold factor of 70 mV/decade for a gate length of 70 nm. As measurement and characterization techniques of Si nanowire transistors, UV Raman microscopy was developed to detect phonon frequency and mechanical strain in a single Si NW. We have succeeded in detection of Raman spectrum of a single NW with a very low excitation power of 10 nW while avoiding heating. This technique allowed us to observe systematic dependence of phonon frequency on NW width. To realize atomic force microscope (AFM) metrology for three-dimensional structure, we have developed simultaneous excitation and detection technique of multi-mode vibrations of probe along horizontal and vertical directions. This two-mode vibration technique actually enabled us to detect horizontal atomic force in addition to the vertical surface profile. To measure the potential distribution with nm resolution on an electrically isolated Si NW, we have developed the combined technique of scanning tunneling microscope (STM) with non-contacting AFM by adopting W probe tips fabricated with focused ion beams. This technique enabled us to measure tunneling current image of stripe structures formed on a Si-on-insulator substrate, while observing the topographic structure by the AFM. Several simulation techniques are under development over multi-scale formulations ranging from ab-initio calculation to device simulator with Monte-Carlo carrier transport calculations. For example, the energetics simulation of dopant impurity atoms revieled that B atoms at the NiSi2/Si interface prefer the Si side location to the silicide side, confirming the ability of impurity segregation technique to modify the electrical barrier at the interface. Using the developed device simulator, in which Coulombic interactions were exactly incorporated, the Coulombic interaction between conduction electrons in the channel and those in the high-doped drain region was elucidated to be a major cause of energy relaxation and hence a limiting factor to reduce the ballistic transport efficiency.
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