成果報告書詳細
管理番号20120000000240
タイトル*平成23年度中間年報 省エネルギー革新技術開発事業/先導研究/極低消費電力III-V族化合物半導体CMOSの研究開発
公開日2012/5/10
報告書年度2011 - 2011
委託先名国立大学法人東京大学 住友化学株式会社 日本電信電話株式会社
プロジェクト番号P09015
部署名省エネルギー部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等 (1)研究開発の内容
低消費電力化を実現するためには、CMOSチャネルの電流駆動力を向上させて、回路動作に必要なオン電流を実現できる電源電圧を低減させることが有効である。このような高い性能を発揮しうるチャネル材料としては、InGaAs、InAs、GaSbなどのIII-V族化合物半導体材料が有望である。
本研究開発では、Siプラットフォーム上のIII-V CMOSの実用化に向けて、その基礎となるIII-V CMOSの基盤技術の開発を行い、低電源電圧を実現できるIII-V族半導体材料系を用いたCMOSのポテンシャルを明らかにすることにある。
英文要約Title: Research and Development Program for Innovative Energy Efficiency Technology, Preparatory research phase, Research and Development of Ultra-low Power Consumption III-V compound semiconductor CMOS (FY2011-FY2012) FY2011 Annual Report
In this study, we are developing CMOS using III-V channels on the Si platform for realizing ultra-low voltage operation. In order to realize this device, we have performed the following researches. As for the epitaxial growth technologies of high quality III-V layers, we optimized the growth temperature, the gas flow conditions and the III/V ratio for realizing high quality strained InGaAs films on GaAs/ InP substrates and GaSb films on GaSb substrates. It was found that polishing flaws of GaSb substrates can be an origin of screw dislocations included in GaSb epitaxial layers. An optimized wet etching process for GaSb substrates by an HCl-based solution successfully eliminated the screw dislocations. As for the channel formation technologies of III-V channels on Si, we also developed a wet treatment technology for reducing surface roughness of GaSb, which is mandatory for wafer bonding of GaSb to Si substrates and resulting formation of GaSb-OI channels. HCl surface treatment and following rinsing by isopropyl alcohol reduced the root-mean-square value of GaSb surface roughness down to 0.71 nm over the surface area of 1 um x 1 um, which is sufficient for the wafer bonding of GaSb to Si substrates. As for the gate stack technologies of III-V CMOS, we studied the reduction in EOT for InGaAs gate stacks and ALD process optimization for GaSb MOS interfaces. We inserted ultrathin Al2O3 layers between HfO2 and InGaAs for satisfying both thin EOT and low Dit. It was found that only 2 monolayer Al2O3 is sufficient to maintain low Dit. By utilizing this structure, we realized 1.08 nm EOT InGaAs gate stacks with Ig of 2E-2 A/cm2 at Vg of VFB + 1V. In order to improve GaSb MOS interfaces, we studied the ALD deposition temperature dependence on Dit at Al2O3/GaSb MOS interfaces. It was found that lower deposition temperature can provide lower Dit and that deposition at 150 C improved the interfacial properties, suggesting the importance of the low temperature process for GaSb MOS gate stacks. In order to realize deeply-scaled high performance III-V pMOSFETs, realization of self-aligned S/D with low parasitic resistance is mandatory. For this viewpoint, a salicide-like self-aligned metal S/D process by using Ni into GaSb was studied. It was found Ni-GaSb alloys formed by direct reaction between Ni and GaSb are suitable for S/D in GaSb p-MOSFETs. The Schottky barrier height of Ni-GaSb against p-GaSb was estimated to be roughly 0.2 eV. A GaSb p-MOSFET with Ni-GaSb metal S/D has been demonstrated by employing this self-aligned process at low temperature of 250°C. Normal MOSFET operation with low gate leakage current has been observed.
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