成果報告書詳細
管理番号20120000000259
タイトル*平成23年度中間年報 「省エネルギー革新技術開発事業/先導研究(事前研究一体型)/ストリームデータ処理の高速・低電力化を目指すマーチングメモリの研究開発」
公開日2012/5/10
報告書年度2011 - 2011
委託先名ルネサスエレクトロニクス株式会社
プロジェクト番号P09015
部署名省エネルギー部
和文要約和文要約等以下本編抜粋:1)研究開発の目的
近年スマートフォンなどに代表される画像・音声等のマルチメディアデータを扱う情報端末では膨大なストリームデータを極めて高速に処理することが求められており、現在のストリームデータ処理システムには主にキャッシュシステムが用いられているが、ストリームデータの離散性によりキャッシュ効率の低下から消費電力の増大を招いている。本研究は、ストリームデータ処理工程におけるエネルギーを効率的に低減する為にストリームプロセサアーキテクチャにマーチングメモリの適用を検討する。
英文要約Title : Energy-saving innovation Project of Leading Research of Marching Memory realizing the High Speed and the Low Power Dissipation Processing of the Streaming Data (FY2011-FY2012) FY2011 Annual Report
This research is about the very important for energy-saving technique of the streaming data processing in the multimedia technology field, which makes the power consumption of the streaming data processing reduce effectively. Current processing system for the streaming data processing consists the cache memory which is not suited for the streaming processing and causes the large power dissipation.
The marching memory uses the different architecture of the memory array and the memory cell decoding technique with conventional memories. The data which are inputted to the marching memory are transferred between memory cells sequentially as like as chain without read out until reaching data output portions and outputted to the CPU for the processing. Between two memory cells, which are neighbored, are connected by the very short bit-line for the data should be transferred. The shortened bit-line makes the data transferred directly without reading out and amplified by the sense-amplifier and re-writing operation. And the decoding operation is not needed by the single destination architecture. These are the reasons that the marching memory realizes the high speed data transfer and reduction of the power dissipation.
The memory cells of marching memory are required several features;
1.The memory cell data should be storage temporarily or continuously.
2.The memory cell data should be transferred to the neighboring memory cell without data collision.
The basic memory cell structures are dynamic type, the data are stored in the capacitor temporarily, and static type, the data are maintained by the feedback loop during activation period. In order to avoid data collision during data transferred the delay element is included for the data delayed and take some time until reaching to the neighboring memory cell or the combine of the master memory cell and slave memory cell and controlled by the non-overlapped two-phase clocks, called as the master/slave control.
The memory array of marching memory is constructed memory cells mentioned above which are forming square. The memory cell which is along the bit-line direction are connected with shortened bit-lines. In this memory array the control signals are inputted to all memory cells, are generated by the simple clock generator which is different from the complex decoding circuit in the conventional memories. Another control signal is the activation signals for the activated marching memory array. This causes a fast clock generation faster than conventional memory decoding operation.
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