成果報告書詳細
管理番号20120000000804
タイトル平成23年度中間年報 極低電力回路・システム技術開発(グリーンITプロジェクト)
公開日2012/7/10
報告書年度2011 - 2011
委託先名株式会社半導体理工学研究センター 国立大学法人東京大学 学校法人慶應義塾
プロジェクト番号P09003
部署名電子・材料・ナノテクノロジー部
和文要約「和文要約等以下本編抜粋:」
1. 研究開発の内容及び成果等
1.1 ロジック回路技術開発
平成23 年度は、前年度に開発した極低電圧でのロジック回路動作課題を解決する候補技術の40nm 要素回路TEG の測定を進めるとともに、測定結果の解析と新たに判明した課題に対する改善技術の検討や40nm 大規模回路TEG の開発を進めた。提案技術による低電圧化により、16bit 整数演算TEG(40nm CMOS)の評価結果から、最終目標である電力1/10、エラーレート1E-10 以下の達成を確認した。
英文要約Title: Extremely Low-Power Circuits and Systems Technology Development Project (Green IT project) (FY2009-FY2012) FY2011 Annual Report

1. Extremely low voltage logic circuits:
A low power 16-bit integer unit has been designed using our low voltage D flip-flop, and fabricated in 40 nm CMOS. Measurement results achieved the final targets; 90% power reduction and error rate less than 1E-10. For further demonstration, a 32-bit MCU core has been designed with newly developed fine-grain VDD architecture. Measurement results showed 0.5 V correct operations.
2. Memory circuits for extremely low power consumption:
SRAM macro with a newly proposed circuit technique that effectively uses non-selected bit line charges has been fabricated. The fabricated macro achieved the final target of reducing the power consumption to 1/10.
8T SRAM macro with stable low power half select operation has been fabricated. Measurement results showed 35% power reduction in write cycles.
3. Extremely low-power analog circuits:
Phase-locked-loop: A one-chip all-digital phase-locked-loop (AD-PLL) has been designed and fabricated in 40nm-CMOS. The fabricated AD-PLL achieved all the final target; power consumption of 0.5uW/MHz at 0.5V between 10MHz and 100MHz, jitter less than 3%, lockup time shorter than 50 clock cycle, successful operation of logic circuit.
Analog front-end: A successive-approximation-register type analog-to-digital converter (SAR-ADC) has been designed. The fabricated ADC operated 1.1uW/MHz with an effective resolution of 7.5bit.
4. Power management and conversion circuits:
A new adaptive power management system has been developed using a digital LDO (Low Droop Output) and a 16-bit integer unit with parity-based error prediction and detection. Adaptive supply voltage control by them achieved a successful operation as low as 0.425V.
5. Chip integration for optimized extremely low power LSI:
To achieve final goals, it has been decided to set up two test chips; A-chip a vehicle to challenge the theoretical limit and B-chip a large scale vehicle that substantiates the utility of the circuit technologies developed in this project. Architecture designs have been completed, and the specific designs of prototype chips were started.
6-A. Short-millimeter-wave wireless: A transmitter architecture with ASK modulator and without power amplifier was proposed. Using the architecture 135GHz wireless communication chipset was fabricated and 10Gbps wireless communication speed was realized.
6-B. Chip-to-chip non-contact interfaces: Low-voltage pulse-based inductive coupling transceiver with clock and data recovery (CDR) circuit has been developed. The fabricated chip achieved data rate of 900Mbps even under the existence of noise. The power consumption was 5.8mW, which corresponds to the energy efficiency of 6.4pJ/bit.
6-C. Low power wireless: A 315MHz injection-locked OOK transmitter and a power- gated receiver front-end have been developed. The transmitter achieved 11uW power consumption. The proposed power-gated low noise amplifier achieved the lowest power consumption of 8.4uW and 20.5dB gain.
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