成果報告書詳細
管理番号20120000000850
タイトル*平成23年度中間年報 低炭素社会を実現する超低電圧デバイスプロジェクト
公開日2012/7/11
報告書年度2011 - 2011
委託先名超低電圧デバイス技術研究組合
プロジェクト番号P10023
部署名電子・材料・ナノテクノロジー部
和文要約和文要約等以下本編抜粋:
(1)研究開発項目
「ロジック集積回路内1次メモリを対象とした、高集積・高速特性・高書き換え耐性などの機能を 有する超低電圧・不揮発デバイスの開発」
1) 磁性変化デバイス、プロセス開発
新規に磁性膜スパッタ装置を導入し、装置立ち上げ、装置の安定稼働、磁気/電気特性の再現性確保などの検討をまず行い、その後、今年度目標である磁性変化デバイス(Magnetic Tunnel Junction、MTJ)の基本構造決定に向けた磁性膜の開発と、多値化に向けた新しい多層デバイス構造を実現するための、要素プロセスの検討を開始した。磁性膜としては東北大学で提案されたCoFeB界面垂直材料を、低電力化に有利な我々の独自構造であるトップピン構造に適用した基本構造を決定した。
英文要約Report on the “Ultra low voltage device project for low-carbon society”

Reduction of power of ICT and electronic equipment is a key issue to achieve a low-carbon society. The Low-power Electronics Association & Project (LEAP) was established on May 21, 2010, and the “Ultra low-voltage device project for low-carbon society” was started on Aug. 6, 2010. The project aims to develop new non-volatile memories and switches and new basic technologies such as low-resistive nano-carbon interconnects and SOI MOSFETs with small Vth variability. An STT-MRAM for embedded cache memories in low-power LSIs was developed, utilizing a top-pinned magnetic tunnel junction combined with the perpendicular anisotropy of CoFeB. Also, a basic integration process flow was designed and verified in MRAM devices on 300-mm wafers. A new negative-resistance-read scheme with robustness against disturbance was developed to realize low-power operation. In phase-change memory, the electrical resistances of Ge2Sb2Te5 and interfacial materials were increased by doping, which is expected to reduce the operating power of PCM to 1/2. A resistance TEG of Ge2Sb2Te5 with a W electrode of 50-nm diameter was fabricated, resulting in a resistance ratio of more than 1000. To develop a cross-point cell, a diode with a poly Si pin junction was made. An atom switch using a polymer solid electrolyte for a reconfigurable logic array was developed. A low programming voltage of 2 V and high OFF-state reliability was verified in a three-terminal atom switch. The feasibility was evaluated in a 1k-bit array and small voltage distributions with high off/on resistance ratio were demonstrated. To measure the variability of the electrical properties, 1-Mb memory macros and switch arrays were designed. A 4 kb switch array for evaluating the OFF-state reliability was also designed. High-density carbon nanotube bundles (1-2×1011/cm2) were grown on 300-mm Si wafers with TiN conductive catalyst sub-layers. High aspect ratio (AR) contact hole TEGs (AR=10,100nmD) were fabricated and CNT bundles were successfully grown from the bottom of the holes with AR=10. Graphene for horizontal interconnect structures with four terminal electrodes was fabricated by electron-beam lithography, and sheet resistance of 300ohm/sq was shown. The structure and fabrication process of a new SOI CMOS, SOTB (silicon on thin buried oxide) for 0.4V operation, was developed. Small variability (4sigmaVth =40.8mV) and 0.4-V operation of an SRAM cell were demonstrated. A hybrid structure combining SOTB and the conventional bulk CMOS was developed. Moreover, a circuit-design platform including standard cells optimized for SOTB was developed, and test circuit layouts were designed. The front-end process was performed in a production line, and the backend process was done in the AIST super clean room. Therefore, a 65-nm-node BEOL platform, featuring a design tool such as an OPC model, a PDK, and common evaluation circuits for BEOL devices using a variety of new materials and structures, was successfully developed.
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