成果報告書詳細
管理番号20120000001083
タイトル*平成23年度中間年報 立体構造新機能集積回路(ドリームチップ)技術開発
公開日2012/10/20
報告書年度2011 - 2011
委託先名技術研究組合超先端電子技術開発機構
プロジェクト番号P08009
部署名電子・材料・ナノテクノロジー部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等
半導体製品の更なる性能向上を図るため、二次元的な微細化に加えて、三次元的なチップ積層構造を採用することにより、高集積化、配線遅延低減、低消費電力化や、開発期間の短縮を実現することが可能になる。
英文要約Title : Development of Functionally Innovative Three-dimensional Integrated Circuit (Dream Chip) Technology (FY2008-FY2012) FY2011 Annual Report
(Cooling, Stacking and Bonding Technology) High accuracy thermal conductivity estimation for ultra-thin 3-high stack structure having Cu-TSV was confirmed by using both simulation and TEG evaluation. Cooling structure design of ranging system for automotive driving assist application was done. 10um pitch bump-bump interconnect was demonstrated by stacking daisy chain TEG (TV10) having 11,520 micro-bumps which alignment accuracy was less than +/-0.6um without any solder bridges. This is a result of "On Time Alignment" technology and Low pressure (=<1N) thermal-compressive interconnect technology. (Thin Wafer Technology) For wafer thinning process with glass based wafer support system which wafers having TSVs and micro-bumps, TTV (Total Thickness Variation) control ability were confirmed around 1.35um (target =<2.0um) after CMP by optimizing glue layer thickness control. Thin wafer backside treatments (stress relief) affecting Cu contamination diffusion were confirmed by C-t analysis using wafers which backside were covered by Cu. (3D Integration Technology) For design, electrical modeling of TSV, low power interface circuits, synchronization scheme among slices were proposed and low noise power lane design were proposed. For process, W2W stacking with high accuracy placements and Via-Last forming for 3-laysers’ W2W stacked wafer was developed. (Ultra-Wide Bus SiP Technology) 3-high stacked structure with Memory Chip + Si-Interposer + Logic Chip was designed by DfT consideration and with redundancies. They were fabricated, assembled, tested and 4K IO operations were confirmed. (Analog/Digital Hybrid SiP Technology) It was confirmed by TEG that TSV having high permittivity liner can work as a De-coupling Capacitance. Simulation results indicated that appropriate design of the interposer’s Power Distribution Network with TSVs for De-Coupling Capacitance has flat and stable low- impedance characteristics. Imaging system with CIS, CDS, ADC and IF chip were designed and fabricated as a demonstrator for analog/digital hybrid system. Each chip was evaluated individually and confirmed their functions. (Heterogeneous 3D Integration Technology) 3D stacking system was designed with elements such as tunable filter by LTCC, MEMS switch and control IC. Tunable filter indicated wide range and low insertion loss which are WW top level. MEMS switch operation was confirmed after attaching onto LTCC and covered by cover chip that its operation is identical as individual chip level.
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