成果報告書詳細
管理番号20130000000129
タイトル*平成24年度中間年報 省エネルギー革新技術開発事業 先導研究 極低消費電力III-V族化合物半導体CMOSの研究開発
公開日2013/4/27
報告書年度2012 - 2012
委託先名国立大学法人東京大学 住友化学株式会社 日本電信電話株式会社
プロジェクト番号P09015
部署名省エネルギー部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等 (1)研究開発の内容
低消費電力化を実現するためには、CMOSチャネルの電流駆動力を向上させて、回路動作に必要なオン電流を実現できる電源電圧を低減させることが有効である。
英文要約Title: Research and Development Program for Innovative Energy Efficiency Technology, Preparatory research phase, Research and Development of Ultra-low Power Consumption III-V compound semiconductor CMOS (FY2011-FY2013) FY2012 Annual ReportIn this study, we are developing CMOS using III-V channels on the Si platform for realizing ultra-low voltage operation. In order to realize this device, we have performed the following researches. As for the epitaxial growth technologies of high quality III-V layers, we optimized the growth condition of InAs on InP, InGaAs on GaAs, and InGaSb on GaSb for channel layers, InAs on GaSb for MOS interface passivation, GaSb on InAs and AlSb on GaSb for wafer bonding processes. The surface flatness of the InAs layers on InP was improved. Also, the growth condition for thinning InAs layers on GaSb without losing thickness uniformity was developed to realize superior MOS passivation for GaSb. As for the channel formation technologies of III-V channels on Si, we developed the fabrication process of the direct wafer bonding for GaSb-On-Insulator on Si and InGaAs-On-Insulator on GaSb. The GaSb-On-Insulator substrates on Si have been fabricated by direct bonding between GaSb grown on InAs substrates and Si substrates with Al2O3 buried oxides, followed by etching the InAs substrates using H2SO4- and C6H8O7-based chemical solutions. The InGaAs-On-Insulator substrates on GaSb have been fabricated by direct bonding between InGaAs grown on InP and GaSb substrates with Al2O3 buried oxides, followed by etching the InP substrates using HCl-based solutions. As for the gate stack technologies of III-V CMOS, MOS interface properties of Al2O3 and HfO2/InGaAs gate stacks were studied. In particular, the impact of the gate electrodes was examined. It was found that Pd gate electrode provides better interface properties in the HfO2 gate stacks than Au and Al electrodes, while the results are opposite in the Al2O3 gate stacks. It was also found that InAs passivation is effective in improving Al2O3/GaSb MOS interface properties. In order to realize deeply-scaled high performance III-V nMOSFETs, we developed a plasma cleaning technology for Ni-InGaAs surfaces in order to reduce the contact resistance, resulting in the contact resistance of as low as 5e-8 ohm*cm-2 between Al/Ti and Ni-InGaAs. We have demonstrated 20-nm-channel length InGaAs(InAs)-on-insulator nMOSFETs on Si substrates by using wafer bonding and Ni-InGaAs source/drain combined with the newly-developed surface cleaning technology. Here, the gate stack was composed of Ta and Al2O3 (5 nm) for In0.3Ga0.7As/InAs/In0.3Ga0.7As quantum well channels. These devices have exhibited the on-current of as high as 2.38 mA/um at gate voltage of 2 V and drain voltage of 0.5 and the trans-conductance of as high as 1.95 mS/um at drain voltage of 0.5 V. As for the development of III-V pMOSFETs, the origin of the high source/drain resistance has been examined. It was found that GaSb substrates near gate edge are etched off during the HCl etching of unetched Ni after Ni-GaSb source/drain formation and that the large series resistance exists between GaSb inversion layers and the Ni-GaSb regions.
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