成果報告書詳細
管理番号20130000000464
タイトル*平成24年度中間年報 低炭素社会を実現する超低電圧デバイスプロジェクト
公開日2013/10/1
報告書年度2012 - 2012
委託先名超低電圧デバイス技術研究組合
プロジェクト番号P10023
部署名電子・材料・ナノテクノロジー部
和文要約
英文要約Title: Ultra Low-voltage Device Project for Low-carbon Society (FY2010-2013) FY2012 Annual Report

This report summarizes the achievement in fiscal 2012 of the “Ultra low-voltage device project for low-carbon society”. The project started on Aug. 6, 2010 with the purpose of developing new non-volatile memories, switches as well as new basic technologies such as nano-carbon interconnects with low-resistance and SOI MOSFETs with small threshold voltage (Vth) variability for low voltage operation of integrated circuits below 0.4V.
An STT-MRAM for embedded cache memories was developed, utilizing a top-pinned magnetic tunnel junction combined with the interface perpendicular magnetic anisotropy of CoFeB. Switching current of 50–100 uA at 0.4 V was achieved. By inserting a CoFe seed layer between MgO and CoFeB layers, the crystalline quality of the stacked layer was much improved and abrupt interface was realized at MgO/CoFeB, which resulted in 10-year lifetime of MgO barrier and 1016 write and read cycles. From these results, we verified that the STT-MRAM is suitable for non-volatile cache memories.
A single-bit PCM (Phase Change Memory) device with a heat diffusion suppression layer was developed and the fabricated devices exhibited power consumption 1/10 of that of the conventional PCM, indicating that the device would show prospective performance such as data transfer rate of 200MB/s consuming only 200mW. A GeTe/Sb2Te3 super-lattice film was developed and the fabricated device realized memory operation at 70uA. This is equivalent to the operation energy as low as 3.5pJ. A cross-point cell device for PCM, comprising of a silicon diode and the super-lattice film, exhibited successful memory read-write performance.
An optimized 3-terminal atom-switch device for reconfiguration of logic circuits using polymer-solid-electrolyte (PSE) and alloyed electrodes was developed by using Cu-alloy and RuTa electrodes to decrease the variability for switching. 2-bit full adder and 4-bit synchronous counter were successfully mapped on 3x3 programmable logic cells using the 3-terminal atom switch. Newly developed cluster packing and placement/routing tool was used to obtain configuration data from an arbitrary RTL description.
In low resistivity interconnect development; carbon nano-tube (CNT) bundles were successfully grown from the bottom of vias with 89 nm in diameter and 17.5 in aspect ratio. Resistance of graphene was measured using stripped graphene sheets with minimum width as narrow as 25 nm. Sheet resistance value of 23ohm/square was obtained for grapheme with 92-nm width. To further decrease the resistivity of multi-layered graphene resistance, Br doping was performed and the resistivity of 4-8 uohmcm (0.1-0.2 ohm/square) was experimentally obtained. For horizontal interconnect, graphene layers on damascene interconnect structure with a catalytic metal is under way using 300 mm wafers.
A new SOI CMOS, SOTB (silicon on thin buried oxide), was fabricated and proved favorable on-current and small parameter variability around the whole area of 300-mm wafer. Measurement of a million MOSFETs demonstrated small Vth variability of ±0.09 V at ±5 sigma. A 2Mb SRAM was verified to be fully operable at the applied voltage as low as 0.37 V. A design and test platforms have been simultaneously developed. A design verification result showed that a circuit built with the SOTB would perform 20-50 MHz clock frequency at 0.4 V, implying 2.5 times more energy efficient. In addition, an MCU chip with CPU core, SRAM and interface circuits was designed and implementation was completed.
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