成果報告書詳細
管理番号20140000000687
タイトル*平成25年度中間年報 ノーマリーオフコンピューティング基盤技術開発
公開日2015/1/31
報告書年度2013 - 2013
委託先名株式会社東芝 ルネサスエレクトロニクス株式会社 ローム株式会社
プロジェクト番号P11001
部署名電子・材料・ナノテクノロジー部
和文要約
英文要約Title: Development of Normally-off Computing Technology (FY2011-FY2015) FY2013 Annual Report (Toshiba Corporation, Renesas Electoronics Corporation, Rohm Co., Ltd, Univ. of Tokyo)

This project is going to develop as following,
(1) Power control technology to utilize the next generation non-volatile element.

(1)-1 Technology for low power portable information terminal with high speed, low non-volatile memory system. (Toshiba Corporation)
(1)-1-1 Development of high speed and low power non-volatile RAM:
Advanced MTJs having perpendicular anisotropy and low saturation magnetization to exhibit low current and fast switching having 100fC were developed. And advanced fast and low power 1Mb MRAM circuits were fabricated in 65nm CMOS technologies and advanced MTJ integrations.
(1)-1-2 Development of high speed and low power non-volatile cache memory circuit and system:
Using nonvolatile cache memory of MRAM developed in (1)-1-1, new memory hierarchy with hybrid SRAM/MRAM was designed. New ultra-fast power gating scheme for it was also proposed, which can practically reduce total power of processor to less than 10% of conventional one.

(1)-2 Technology for low power sensor networks in smart city (Renesas)
(1)-2-1: Using the Normally-off evaluation environment for sensor network system, we made test programs including sensor drivers with Ritsumeikan University we confirmed power consumption is reduced.
(1)-2-2: A sample test program has been developed for an on-demand traffic system to get system log information. Referring to the information, we started to consider task scheduling with The University of Tokyo.

(1)-4 Ultra low-power wearable biosignal sensor networks for healthcare applications (Rohm)
(1)-4-(1): Novel 6T-4C shadow memory architecture was proposed. The proposed technique utilizes the ferroelectric capacitor and the store/recall circuits to reduce its power overhead.
(1)-4-(2): We proposed a power reduction technique for the sensor front-end of an ECG SoC. A robust instantaneous heart rate detection algorithm contributes to mitigate the performance requirements of analog circuits.
(1)-4-(3): We developed a prototype system using the proposed ECG SoC, which consists of analog front-end, ADC, Cortex-M0 core, and FeRAM. The prototype system consumes 38 uA including the proposed SoC, an accelerometer, a NFC tag IC, and LDOs.


(2) Research on computing to realize effectively normally-off operation for sustaining future social life

(2)-1 (Renesas)
Renesas made normally-off evaluation fundamental technology as the actual equipment evaluation environment, to get a prospect of 10 times lower power consumption than present system.

(2)-2 (Toshiba)
New power gating scheme for nonvolatile cache memory systems was developed. Using this, power consumption is expected to be decreased to around 1/3 of conventional one. Decrease by 1/10 will be expected by further improvement of memory devices and systems.

(2)-3 (Univ. of Tokyo, Renesas, Toshiba, Rohm) Optimization of Normally-Off Computing: We investigated low-power system architecture which adopts non-volatile memory. We made preliminary evaluations on the effectiveness using real applications. Evaluation Methodology of Normally-Off Computing: We developed general power model of the proposed system architecture. As the model is very general, it can be used to explore desired property of non-volatile memory and applied to other system architectures with new non-volatile memory.
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