成果報告書詳細
管理番号20140000000608
タイトル*平成25年度中間年報 低炭素社会を実現する超低電圧デバイスプロジェクト
公開日2015/2/19
報告書年度2013 - 2013
委託先名超低電圧デバイス技術研究組合
プロジェクト番号P10023
部署名電子・材料・ナノテクノロジー部
和文要約
英文要約Title: Ultra Low-voltage Device Project for Low-carbon Society (FY2010-2014) FY2013 Annual Report

This report summarizes the achievements in fiscal 2013 of the “Ultra low-voltage Device Project for Low-carbon Society”.
 An STT-MRAM was developed, utilizing a top-pinned magnetic tunnel junction combined with the interface perpendicular anisotropy of CoFeB. A size variation of MTJs was reduced to 4.1 nm in 3σin a local area by process optimization. The stability of small MTJs in terms of stray magnetic field was improved down to 35 nmφ by using a newly developed pinned layer. The switching current was reduced to 15 uA by using light oxidation of MTJs. In addition, a SPICE model of the MTJ was refined.
A “topological switching random access memory (TRAM)” was developed. First principle calculations showed the movement of Ge atoms and corresponding resistance change in GeTe/Sb2Te3 super-lattice was enhanced by charge injection. It was observed that the super-lattice structure was maintained after 1M program and erase cycles, and a high resistivity ratio is kept even after 100M cycles with a high quality GeTe/Sb2Te3. A reset current of less than 1/5 that of the conventional PRAM was measured in TRAM. Furthermore, a set-speed of 10 ns, the fastest ever reported, was obtained. 1T-1R TRAM TEGs were fabricated and reset voltage of 2V, which was less than 1/2 that of the conventional PRAM, was measured.
 Leakage current and program voltage variation of atom switches were improved using newly developed integration process, including a pre-etching process before a PSE film deposition. A 16-bit ALU was implemented and demonstrated on a 24x24 programmable-logic array including atom switches for both routing switches and configuration memories. The proposed programmable-logic array performs 61% active power saving and 3 times faster operation.
 Intercalation doping for narrow graphene wires was developed to obtain a low resistivity of 13 mWcm at 800-nm wide line. Selective growth of graphene on a Ni damascene array at low temperature was demonstrated on 300-mm wafers. Crystal quality measured by G/D ratio of low-temperature CVD graphene was improved resulting in increase of G/D ratio from 1 to over 10. CNT-via fabrication process on 300-mm wafers became available.
 SOTB (Silicon on Thin Buried Oxide) fabrication process was improved to a pre-production level. Especially, a silicon epitaxial growth on the source/drain region was developed by using a newly introduced epitaxial growth apparatus. As the result, the operating yield of SRAM at 0.4 V of 91% was achieved. Soft error immunity of SOTB was proved to be one to two orders of magnitude higher than bulk. Many SOTB circuits : a micro-controller, accelerator, FPGA, PLL, power supply can operate at around 0.4 V with a power consumption of about one order of magnitude lower than that of corresponding bulk circuits. The micro-controller CPU has a record low energy consumption of 13.4 pJ at 0.35 V and 14 MHz.
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