成果報告書詳細
管理番号20150000000585
タイトル*平成26年度中間報告 SIP(戦略的イノベーション創造プログラム) 次世代パワーエレクトロニクス 将来のパワーエレクトロニクスを支える基盤研究開発 材料科学に基づく4HーSiC上の高品質ゲート絶縁膜形成手法の研究開発
公開日2015/8/4
報告書年度2014 - 2014
委託先名国立大学法人東京大学
プロジェクト番号P14029
部署名電子・材料・ナノテクノロジー部
和文要約
英文要約Title: Cross-ministerial strategic innovation promotion program (SIP),“Next-generation power electronics”, Research and development of material-science-based process design for high quality gate stack formation on 4H-SiC (FY2014-2015) FY2014 Annual Report

(1) High-quality MOS interface formation on 4H-SiC (0001) : control of annealing process after thermal oxidation
The post-oxidation anneal (POA) process was found to be an effective way to reduce Dit of 4H-SiC MOS interface. Thermal oxides were grown on (0001) wafers by dry-O2 oxidation, followed by POA in O2 or N2 ambient at lower temperature. The POA in O2 was found to be more effective to reduce Dit in near conduction band edge energy region than that in N2, probably because O2 has a role to annihilate the oxygen deficiency or to remove the carbon-related byproducts near the interface during POA. We also found that there is an appropriate range of POA time. Dit decreases in the first stage but turns to increase in the latter stage, probably because of the competition between defect annihilation and generation, considering that non-negligible SiC oxidation at the interface at low temperature will increase the interface defects. These results clarify that MOS interface with Dit<10^11 cm^-2eV^-1 is attainable by tuning POA conditions for our thermal oxides on 4H-SiC (0001).

(2) Advanced characterization of MOS interface quality : a new quantitative evaluation method of near-interface oxide traps
Quantitative characterization methods of near-interface trap (NIT) has not been established. We can trace the de-trapping process of electrons from NITs by observing the transient behavior of capacitance of MOS capacitor (C-t measurement) after a sudden change of gate bias. Because of the wide distribution of the relaxation time due to the variation of depth of traps from the interface, the obtrained C-t curves were fitted by extended Debye function. A MOS capacitor with relatively poor interface property was employed as a test sample. The amount of released charges from NITs was determined from the fitting parameters. As for the effective density of states caused by NITs, around 10^12 cm^-2eV^-1 was estimated for the shallow location (shorter relaxation time), while around 10^11 cm^-2eV^-1 was estimated for the deep location (longer relaxation time). This method is considered as one of the evaluation techniques of NIT density.

(3) Validity of our approaches : Demonstration of mobility improvement in lateral MOSFETs
On p-type 4H-SiC (0001) wafers, lateral MOSFETs were fabricated using our MOS fabrication processes. The devices employing the process with appropriately tuned POA conditions, resulted in a field effect mobility of 37 cm^2V^-1s^-1 at maximum. Even without any additional passivation processes of MOS interface, the obtained mobility value seems to be no less than the ones frequently reported for typical MOSFETs with NO-treatments. This result demonstrates the validity of our approach to design the MOS fabrication processes for the improvement of MOSFET performance.
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