成果報告書詳細
管理番号20150000000616
タイトル*平成26年度中間年報 低炭素社会を実現する超低電圧デバイスプロジェクト
公開日2015/8/4
報告書年度2014 - 2014
委託先名超低電圧デバイス技術研究組合
プロジェクト番号P10023
部署名電子・材料・ナノテクノロジー部
和文要約
英文要約Title: Ultra Low-voltage Device Project for Low-carbon Society (FY2010-2015) FY2014 Annual Report

This report summarizes achievements in fiscal 2014 of the “Ultra low-voltage device project for low-carbon society”.
As to STT-MRAM development, the variation of MTJ resistance was reduced to 16% in 3σin a local area by process optimization. The number of leaky MTJs was drastically reduced by a new MgO fabrication process. The MgO also showed enough breakdown characteristics and infinite cycling time. Macro chips with embedded 1 M-bit STT-MRAMs were fabricated. Short read and write time, and small cell size were demonstrated. As a demonstration of the STT-MRAM application, the fabricated macro chip was implemented in a battery- and sensor-less drive recorder system.
A GeXTe1-X/Sb2Te3 (X < 0.5) TRAM showed a reset voltage of less than 60% that of previously reported GeTe/Sb2Te3 TRAM in a 1R (Resistance) TEG. The GeXTe1-X/Sb2Te3 layer was deposited on a Sb2Te3 bottom layer, and 1T-1R memory cells with a 60-nm bottom contact electrode were successfully fabricated. A statistical analysis of a 16-kb TRAM showed non-volatile recording at 2.0V. Furthermore, a 2-Mb TRAM macro with read and write peripheral circuits was verified to operate. A FBM analysis also demonstrated that the TRAM macro operated at 2.3V, although there were failure bits presumably caused by the peeling of the super-lattice film.
Fast and low voltage programming of Cu atom switch was demonstrated in a 1-Mb switch array. A 64x64 programmable-logic cell array including a 9.2-Mbit atom switch, as the routing switch and configuration memory, was developed. A 16-bit arithmetic logic unit, which is a building block of the micro-controller unit, was implemented to compare the speed and power consumption with a commercially available low power field-programmable gate array. The proposed programmable-logic array exhibited 13% active power saving and 2.5 times faster operation. Zero sleep power was also demonstrated.
 Crystal quality (G/D ratio in Raman shift spectrum) of low-temperature (LT) CVD multi-layer graphene (MLG) was improved up to 30. The LT-MLG was doped by MoCl5 intercalation resulting in obvious Fermi level shift detected by Raman G peak shift. LT-MLG/Ni damascene wiring arrays with half-pitch of 30-nm and length of 0.7-mm were successfully fabricated on 300-mm Si wafers. Large scale CNT-via-chains (10-20,000 vias) were fabricated on 300-mm Si wafers.
 A SOTB CMOS process reached to a production level, resulting in 95% operating yield of SRAM at 0.4 V. Three process options were developed: ULV for <0.4-V operation, LV and ULSB for ultralow leakage (100 nA with and w/o back bias, respectively). The evaluation of circuits and chips such as a micro-controller, accelerator, FPGA, ADC, power supply revealed that SOTB circuits operated with one order of magnitude lower power than that for bulk circuits. The micro-controller with an atom-switch programmable ROM and an on-chip back-bias generator recorded energy consumption of 14.0 pJ at 0.4 V and 16 MHz, and standby current of 108 nA.
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