成果報告書詳細
管理番号20150000000631
タイトル*平成26年度中間年報 次世代スマートデバイス開発プロジェクト 車載用障害物センシングデバイスの開発
公開日2015/12/25
報告書年度2014 - 2014
委託先名株式会社デンソー ラピスセミコンダクタ株式会社 独立行政法人産業技術総合研究所
プロジェクト番号P13005
部署名電子・材料・ナノテクノロジー部
和文要約
英文要約Title: R&D Project for the Next Generation Smart Device / Development of an Obstacle Sensing Device Available for Vehicles

The aim of this project is to develop ranging sensor devices which can detect pedestrians and vehicles night and day. To realize this, photo detectors installed in an array and signal-processing circuits are implemented in three dimensions. By doing so, the effective area of the photo detectors is enlarged and electrical wiring length shortened, which improves the sensitivity and wide range accuracy. This year’s achievements are given below.

1. Ranging Sensor Device and Circuit Development
  We have created an experimental TEG of a light-receiving device which provides 3x the sensitivity of prior versions. We have also developed a prototype of the signal processing circuitry, performed an operation check, and verified the feasibility of the ranging sensor.

2. 3D Integrated Design Environment
  We have developed a design flow and libraries for 3D-IC design, and will use it for a trial design of the sample circuits. We have implemented the fundamental functionality of the integrated design tool, i.e. IC design data interface and interchip connection verification.

3-1. Printed TSV Development
 We have used a prototype of the TSV metal filling machine to identify fabrication issues. We have come up with methods to electrically contact the Al wiring layer, prevent the filler from leaving vias, cut residual substance after filling, and have begun vetting the metal filling materials.

3-2. Printed Bump Development and Wafer Warpage Reduction
We have created specifications for 4 μm diameter bumps and used a sunken printing technique to create the bumps and perform an initial evaluation. Openings for the bumps on the top of the chip were added to alleviate deformation and misalignment issues.

3-3. TSV Process Integration
 The process evaluation result performed the last year was reflected and a design of process TEG and manufacturing were performed. We have designed a TEG to evaluate KOZ and which uses a Cu via fill process for the TSVs.

3-4. Low-Stress Chip Stack and Connection Development
 We have been able to control the electrical resistance variability to less than 10% between daisy-chain stacked chips connected with 4 μm diameter micro-bumps. Employing an electrostatic chuck allowed us to minimize substrate deflection during pressurization, enabling the bonding of ultra-thin chips.

4-1. 3D System Inspection
We evaluated a probe card for the microbumps and have conducted a feasibility study on non-destructive diagnosis methods for TSVs using a state-of-the-art X-ray system. Technological issues to detecting failure modes in flip chip joints and TSV metal have been identified.

4-2. 3D System Evaluation
We have continued to develop analysis and evaluation methods that take into account the various electrical, thermal and mechanical needs of the system. We have put together an analysis framework and have designed test circuits to evaluate the performance of the TSVs.
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