成果報告書詳細
管理番号20160000000678
タイトル*平成27年度中間年報 SIP(戦略的イノベーション創造プログラム)/次世代パワーエレクトロニクス SiCに関する拠点型共通基盤技術開発 SiC次世代パワーエレクトロニクスの統合的研究開発
公開日2016/8/5
報告書年度2015 - 2015
委託先名国立研究開発法人産業技術総合研究所 国立大学法人京都大学 国立大学法人大阪大学  一般財団法人電力中央研究所
プロジェクト番号P14029
部署名IoT推進部
和文要約
英文要約Title : Cross-ministerial Strategic Innovation Promotion Program (SIP) / Next-generation power electronics / Consistent R&D of next-generation SiC power electronics (FY2014-FY2016) FY2015 Annual Report

1. Development of Next Generation SiC Wafer Technology; The development of the impurities control technology for 4H-SiC bulk crystal growth was performed using the co-doping method. For n-type growth 3 inch wafers with the resistivity lower than 10 mohm-cm were developed using the N-Al or N-B co-doping. The high growth rate of 2.4 mm/h was achieved under the N doping of 2.1×E19/cm3. For p-type growth 4H-SiC wafers with the resistivity lower than 100 mohom-cm was obtained without the polytype inclusion by the Al-N co-doping. We also investigated the suppression of stacking faults in heavily N doped wafers and revealed the effectivness of co-doping. For the development of the epi-(epitaxial) wafers for the ultrahigh voltage SiC power device, we focused on the bipolar degradation and revealed it could be suppressed by using highly N doped layer as carrier recombination enhancement layer. Controlling initial epi-growth conditions, the threading BPD density was reduced less than 0.5/cm2 in 3 inch wafer. We also suppressed the generation of epi-defects of 250um thick epi-layer less than 0.5/cm2. 2. Development of Next Generation SiC Device Technology; As for new structure unipolar device, super-junction (SJ) structures over 20um in depth was achieved by using the processes of trench formation, backfilling epi-growth and flattening of backfilled wafer. In order to elucidate physics in electrical properties at the SiC/oxide interface, TEG chips were fabricated under several oxidation conditions. New evaluation techniques e.g. evaluation methode for Vth shift under actual AC stress conditions were developed and used. Ultra-high-temperature dry oxidation was conducted. It was found that interface properties of SiCMOS devices were significantly improved by rapid cooling under an inert atmosphere. As for bipolar device, 20kV break down voltage SiC-PiN diode was successfully achieved. Improving the trade-off relation between SW loss and RonA of 13-20kV class PiN diode and SiC-IGBT, hole injection control method was found to be essential. Bipolar degradation was investigated by mechanism analyses and its beginning was successfully suppressed up to 600A/cm2. The electron and hole impact ionization coefficients were accurately determined in the wide temperature range from 240 K to 573 K, to predict the breakdown voltage of any SiC devices precisely. 3. Development of Next Generation SiC Module Technology; The design and durability evaluation technologies of the high chip current density (1kA/cm2 class) power module are being focused on. The modules use 1.2kV class SiC-MOSFETs, and are considered to be used for such as vehicle power converters. 3 designs of power module, which used 250C-class high temperature packaging technology with temperature resistant components, were proposed and tested. The validity of the design was confirmed by the results of 600V-50A switching test at the device temperature of 225C, because the module showed very high switching speed (below 20ns).
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