成果報告書詳細
管理番号20160000000680
タイトル*平成27年度中間年報 SIP(戦略的イノベーション創造プログラム)/次世代パワーエレクトロニクス 将来のパワーエレクトロニクスを支える基盤研究開発 超高次非線形誘電率顕微鏡法を用いたSiC基板材料及びパワーエレクトロニクス素子の高性能化に資する評価技術の開発
公開日2016/8/5
報告書年度2015 - 2015
委託先名国立大学法人東北大学
プロジェクト番号P14029
部署名IoT推進部
和文要約
英文要約Titel:Development of Evaluation Techniques for SiC High Quality Substrates and High Performance Power Electronics Devices Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy.(FY2014-FY2015)FY2015 Annual Report

Silicon Carbide (SiC) is one excellent semiconductor material for power semiconductor application because of its large bandgap. SiC metal-oxide-semiconductor (MOS) field-effect-transistors (FETs) still suffer from severe degradation of channel electron mobility, whose cause is considered as imperfect SiO2/SiC interface. Usually, SiO2/SiC interface quality has been characterized by fabricating MOS capacitor on the sample, which needs additional processes following the oxidation and annealing process. Because, in research & development (R&D) of devices, many times of sample fabrication and characterization are required, characterization technique which is easy and takes short time is effective to shorten the R&D cycle. Previously, it has been reported that scanning nonlinear dielectric microscopy (SNDM), which is one of scanning probe microscopies, gives images which correlated with interface trap density of SiO2/SiC interface. SNDM measurement does not require additional process after oxidation and annealing pocess therefore SNDM is a candidate of easy and sophisticated method for interface quality characterization.In this study, oxidized both silicon-face (Si-face) and carbon-face (C-face) wafers with various post-oxidation-annealing conditions were measured by SNDM and method for evaluating SiO2/SiC interface quality using SNDM is proposed. It was shown that normalized standard deviation of SNDM image was good parameter to evaluate SiO2/SiC interface of Si and C-face. SNDM measurement does not need electrode fabrication to measure C-V curve, but just scan on the oxidized wafer with conductive tip, which is easier and quicker. This technique enables us to quickly examine the effect of process and should effectively reduce the time needed for R&D cycle.
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