成果報告書詳細
管理番号20160000000683
タイトル*平成27年度中間年報 SIP(戦略的イノベーション創造プログラム)/次世代パワーエレクトロニクス 将来のパワーエレクトロニクスを支える基盤研究開発 パワーデバイス実用化を可能とする革新ダイヤモンド結晶成長技術開発
公開日2016/8/10
報告書年度2015 - 2015
委託先名国立研究開発法人物質・材料研究機構 国立大学法人東京工業大学 国立研究開発法人産業技術総合研究所 コーンズテクノロジー株式会社
プロジェクト番号P14029
部署名IoT推進部
和文要約
英文要約Title: Cross-ministerial Strategic Innovation Promotion Program/ Next Generation Power Electronics/ Feasibility Study on the Development of Diamond Crystal Growth for Power Device Applications (FY2014-FY2016) FY2015 annual report
1. Development of high purity diamond growth and impurity doping control technologies (NIMS)
Combining optimization of metallic materials of sample stage and using high concentration oxygen contained source gas, high purity homoepitaxial CVD diamond growth was successfully performed showing nitrogen concentration of 1 ppb.
2. Research on the characterization and suppression dislocation density in diamond (NIMS)
Cathodoluminescence measurements revealed that the dislocations in the CVD layers have been mostly propagating through the epitaxial interface from the substrate and CVD originated dislocations are quite few.
3. Development of CVD reactor for diamond growth with high purity and quality (CORNES Technologies Ltd.)
Diamond CVD reactor with newly designed sample stage was completed and operation test was started. The leakage rate of machine was as small as 1E(-12) Pa m^3/sec which is adequate to give high purity diamond growth. However, out gassing of the new machine prevented to get optimum background vacuum level of less than 1E(-8) Pa and further degassing procedure is in progress.
4. Development of process technology for diamond-power devices
Utilizing submicron-scale etching technique of diamond established through our SIP research, we developed the process technology to fabricate fine structures for vertical-type diamond JFET. Together with this, the fabrication method of submicron-scale alignment-mark was established for electron-beam lithography, which is needed to deposit several lithography-patterns. Moreover, we formed the heavily doped layer on the i-layer in order to improve the electric properties of pin-junction diode.
5-1. Material evaluation due to pin junction
{111}-oriented diamond pin-junction diode was successfully formed with the i-layer thickness of ~200 nm by using the improved growth condition of diamond and process technologies, and measured the current-voltage properties. The diode showed the blocking voltage of 92.5 V that correspond to the blocking electric field of 4.6 MV/cm, which is higher than the other material limits. From the T-CAD simulation of the sample structure, we obtained breakdown electric field of 8 ~ 9 MV/cm at the edge of the mesa-structure and the value is close to the value expected for perfect diamond crystal.
5-2. Formation of diamond junction FET and the device characterization (Tokyo Inst. Tech.)
Towards obtaining high current diamond JFETs, we developed current enhancement technique and vertical diamond JFETs. By operating the device in the bipolar-mode, the current enhancement by a factor of 8-10 was achieved from room temperature to 573 K. For further increase of operating currents, vertical diamond JFETs with selective-grown n+ gates were developed.
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