成果報告書詳細
管理番号20160000000685
タイトル*平成27年度中間年報 SIP(戦略的イノベーション創造プログラム)/次世代パワーエレクトロニクス 将来のパワーエレクトロニクスを支える基盤研究開発 材料科学に基づく4HーSiC上の高品質ゲート絶縁膜形成手法の研究開発
公開日2016/8/5
報告書年度2015 - 2015
委託先名国立大学法人東京大学
プロジェクト番号P14029
部署名IoT推進部
和文要約
英文要約Title: Cross-ministerial strategic innovation promotion program (SIP),“Next-generation power electronics”, Research and development of material-science-based process design for high quality gate stack formation on 4H-SiC (FY2014-2016) FY2015Annual Report
(1) Process development for high-quality MOS interface formation on 4H-SiC
(a) Reduction of near-interface oxide traps at thermally-oxidized 4H-SiC (0001) interface
Since the near-interface traps (NITs) in thermally-grown SiO2 have relatively longer trap/de-trap time constant, they significantly affect the impedance characteristics when measured at low temperature. We examined C-V characteristics at 200K and 300K of two kinds of MOS capacitors on 4H-SiC(0001) fabricated by 1300oC oxidation with or without post-oxidation annealing in O2 at 800oC (O2-POA). We found the hysteresis of C-V curves at low temperature was efficiently suppressed by O2-POA.
(b) Control of MOS interface characteristics on 4H-SiC (000-1) by dry oxidation
Our approach to control 4H-SiC (000-1) MOS interface is to oxidize the surface with “high-temperature mode” reaction where SiO2 + CO direct generation becomes dominant, by tuning the oxidation temperature and oxygen partial pressure (pO2). To suppress the effects of unwanted “low-temperature mode” oxidation, the conditions with low pO2 were employed in this study. The oxidation in 2%-O2 ambient at 1300oC resulted in a MOS capacitors with significantly improved C-V characteristics, compared to the ones for 100%-O2-grown oxide. On the other hand the dilution of oxygen down to 0.1%, resulted in rather deterioration of the characteristics.
(c) Reduction of the fixed charge density at the interface
Improvement of MOS characteristics by hydrogen annealing at high temperature (~1000oC) has been often reported. We found the diluted hydrogen annealing at 1150oC are quite effective to suppress the fixed charge density, for both 4H-SiC (0001) and (000-1) MOS capacitors fabricated with our high-temperature thermal oxidation processes. Especially for (0001) capacitors, we successfully achieved a sufficiently low interface trap density, as low as 1×1011 cm-2, determined from the observed fixed charge density.
(2) Effects of thermal oxidation processes on mobility enhancement of lateral MOSFETs
 Lateral MOSFETs were fabricated on p-type 4H-SiC (0001) epi-wafers, by employing our thermal oxidation processes for gate oxide growth, on three kinds of wafers supplied by different institutes: the University of Tokyo (UT), AIST (A), and Mitsubishi Electric (M). For “UT” samples we achieved field-effect peak mobility as high as 20~35cm2V-1s-1. The values around 30cm2V-1s-1 were repeatedly observed especially after 1%-H2 metallization anneal. The mobility of the sample “M” was not so high as “UT”, but it was significantly higher than that of the standard sample in Mitsubishi Electric with a simple thermally-grown oxide.
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