成果報告書詳細
管理番号20160000000687
タイトル*平成27年度中間年報 SIP(戦略的イノベーション創造プログラム)/次世代パワーエレクトロニクス 将来のパワーエレクトロニクスを支える基盤研究開発 酸化ガリウムパワーデバイス基盤技術の研究開発
公開日2016/8/5
報告書年度2015 - 2015
委託先名国立研究開発法人情報通信研究機構 株式会社タムラ製作所 国立大学法人東京農工大学 新日本無線株式会社 株式会社シルバコ・ジャパン
プロジェクト番号P14029
部署名IoT推進部
和文要約
英文要約1. We developed a process to remove the damaged region formed during Ga2O3 (010) wafer manufacturing. Grinding and lapping induced 50-um-deep and 20-um-deep damaged regions, respectively, and that chemical mechanical polishing caused no damage on the surface. Based on this knowledge, the wafer manufacturing process was optimized to ensure complete removal of the damaged material.

2-1. We succeeded in developing HVPE homoepitaxial growth technology for Si-doped Ga2O3 thin films with an electron density controlled down to 1e15 cm-3. The density of compensating acceptors incorporated in the epitaxial layer was extremely low at less than 1e11 cm-3. It also turned out that the electron mobility was determined by the ideal lattice scattering factors.

2-2. We completed the setup of the MBE machine installed in NICT in FY2014 and established the homoepitaxial growth conditions for flat Ga2O3 (010) layers at a high growth rate (~0.7 um/h).

2-3. We selected sputtered NiO as a first candidate of p-type oxide material for Ga2O3 DMOSFETs and investigated its resistivity and contact resistance as a function of deposition temperature. From experimental results, 200-300degC was determined to be the optimum deposition temperature. The valence band offset at the interface between NiO and Ga2O3 was determined to be 1.76 eV. Finally, we fabricated p-NiO/n-Ga2O3 diode structures that showed rectifying behavior with a turn-on voltage of about 3.3 eV.

3-1. We fabricated Ga2O3 MOSFETs with a gate-connected field plate (FP) for substantial enhancement in off-state breakdown voltage. The transistors exhibited a high drain current density of 78 mA/mm, an off-state breakdown voltage of 755 V, and stable high temperature operation at 300degC. Effective surface passivation and high Ga2O3 material quality contributed to the absence of drain current collapse under pulsed operation.

3-2. Ga2O3 FP-SBDs were fabricated on HVPE-grown epitaxial wafers. The devices showed a high breakdown voltage of 920 V. Next, to characterize the Schottky interface quality, we investigated the temperature-dependent current density-voltage (J-V) and capacitance-voltage characteristics of Pt/Ga2O3 SBDs. In an operating temperature range from 21degC to 200degC, the Pt/Ga2O3 (001) Schottky contact exhibited a zero-bias barrier height of 1.12±0.03 eV with a constant near-unity ideality factor of 1.03±0.01. The J-V characteristics of the SBDs were well-modeled by thermionic emission in the forward regime and thermionic field emission in the reverse regime over the entire temperature range.

3-3. We optimized the deposition conditions of SiO2 thin films. We fabricated vertical MOS diodes using TEOS-CVD and ALD for SiO2 deposition. Post deposition annealing was performed at 600, 800, 1000degC. The capacitance of the TEOS-SiO2 decreased with increasing annealing temperature and saturated at the ideal value, while the ALD-SiO2 showed near-ideal capacitance that changed only slightly with annealing.
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