成果報告書詳細
管理番号20160000000706
タイトル*平成27年度中間年報 次世代スマートデバイス開発プロジェクト 車載用障害物センシングデバイスの開発
公開日2016/8/5
報告書年度2015 - 2015
委託先名株式会社デンソー ラピスセミコンダクタ株式会社 国立研究開発法人産業技術総合研究所
プロジェクト番号P13005
部署名IoT推進部
和文要約
英文要約Title: R&D Project for the Next Generation Smart Device / Development of an Obstacle Sensing Device Available for Vehicles(FY2013-FY2017) FY2015 Annual Report

  The aim of this project is to develop ranging sensor devices which can detect pedestrians and vehicles night and day. To realize this, photo detectors installed in an array and signal-processing circuits are implemented in three dimensions. By doing so, the effective area of the photo detectors is enlarged and electrical wiring length shortened, which improves the sensitivity and wide range accuracy. This year’s achievements are given below.

1. Ranging Sensor Device and Circuit Development
  We have expanded on our single-device work from FY2014 by creating and evaluating an array of light-receiving devices. The FPGA-based prototype of the signal processing circuit has been successfully re-implemented with custom logic in a modern IC process.

2. 3D Integrated Design Environment
  We developed a TSV Process Design Kit (PDK) for our processes (top chip 180 nm, bottom chip 65 nm) and used this PDK to design a test circuit which has been fabricated and evaluated. Prototype tools have been created to test chip interconnectivity and generate models.

3-1. Printed TSV Development
  We have finished vetting the TSV printing process and have also developed improved methods for electrically contact the Al wiring layer and removing residue after filling. We have improved the metal printing equipment to decrease temperature rise/cool times by 50%.

3-2. Printed Bump Development and Wafer Warpage Reduction
  We have created lower-cost combined printed TSVs and 7 micron diameter bumps. This allows for a 30% reduction in time as compared to a traditional plating process. We have created a test device and concluded that there are no warpage problems.

3-3. TSV Process Integration
  We have designed and fabricated a test chip with 20,000 TSVs, obtaining an initial yield of 80%. Specifications have been developed for commercial and industrial applications. Studies are being performed to determine the changes needed to meet the reliability needs of vehicular applications.

3-4. Low-Stress Chip Stack and Connection Development
  We have evaluated the reliability of a TSV and bump test-device using low-CTE underfill that was previously analyzed in FY2014. We have also evaluated two metals to be used as the material for TSVs and investigated the effect of bump material volume on the characteristics of the bump.

4-1. 3D System Inspection
  We have evaluated test samples (20 micron pitch, 5 micron bump) and created specifications for probe cards capable of measuring these devices. We have evaluated our state-of-the-art X-ray system and determined that it is capable of detecting defects as small as 1.5 micron.

4-2. 3D System Evaluation
We have continued to develop analysis and evaluation methods that take into account the various electrical, thermal and mechanical needs of the system and used these methods to design, test and evaluate a device to obtain design guidelines. We are working with JEITA-3D and SEMI to create proposals for international standards.
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