成果報告書詳細
管理番号20100000001205
タイトル*平成21年度中間年報 省エネルギー革新技術開発事業/先導研究/第2世代超薄膜ゲート絶縁膜材料の研究
公開日2010/9/9
報告書年度2009 - 2009
委託先名国立大学法人東京工業大学 独立行政法人産業技術総合研究所
プロジェクト番号P09015
部署名省エネルギー技術開発部
和文要約和文要約等以下本編抜粋:1. 研究開発の内容及び成果等 (1)研究開発の内容 温室効果ガスの排出量の大幅な削減は地球環境の保護の観点から必ず実現しなければならない事であり、国の公約にもなっている。そのためには一次エネルギーから動力・熱・光・電気など二次エネルギーへの変換効率を高めるとともに、製造、交通・運輸、情報・通信、家庭、オフィスなどのあらゆるシステムの動作効率を高めていくことも非常に重要である。本先導研究はEOT=0.5nmやそれ以下においても大きいドレイン電流、高いキャリア移動度を得ることが可能な希土類金属酸化物をベースとしたhigh-k絶縁膜とSiとの直接接合ゲートスタックによる第2世代のhigh-kゲートスタック技術を開発し、EOT=0.5nmの実現可能性を実証することにより第2世代high-kゲートスタック技術が実用化への研究に値することを示すことを最終目標に研究内容を以下のような4つの研究開発項目に分けて先導研究を行っている。
英文要約Title: Leading Research Project for Development of Innovative Energy Conservation Technologies, Development of the Second-Generation Ultrathin Gate-Dielectrics Materials (FY2009-FY2010) FY2009 Annual Report
Reducing the power consumption of large-scale integrated circuits (LSIs) is critically important in order to suppress the emission of the greenhouse gases in various systems. Scaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) devices has been most effective for lowering the operation voltage and thereby reducing the power consumption of the LSIs. However, the gate dielectrics in the present-day MOSFETs are already so thin that further thickness scaling is a very difficult task. In the first-generation high-k gate stacks, which use HfO2-based dielectric materials, an interfacial layer of SiO2 or SiON is inserted between the high-k dielectrics and silicon channel. This interfacial layer is effective to mitigate deterioration of the carrier mobility induced by the high-k dielectrics, however, it also limits the scaling of the equivalent oxide thickness (EOT) of the entire gate stack. Therefore, the second-generation gate stack technology is now required so the high-k layer and Si can be directly contacted without insertion of the interfacial layers, while maintaining good performance of the MOSFET devices. This study aims at development of ultrathin gate-dielectric materials that enable high drain current and carrier mobility in the direct-contact structures. The final goal is to prove that the second-generation high-k gate stack incorporating the direct-contact interfaces is a feasible technology and is worth further investigation toward commercialization.
Tokyo Institute of Technology is responsible for development of such a second-generation high-k gate stack technology with EOT less than 0.5nm. In order to achieve this, key technologies on the controlling of the interface between high-k and silicon direct-contact and also the interface between gate metal and high-k are to be developed. Those developed technologies will be verified by applying them into the fabrication of MOSFETs. In FY2009, a cluster tool consists of 4 chambers; a load/lock chamber, a sputter chamber with 5 targets for metal deposition, an EB chamber with 8 targets for high-k deposition and an in situ thermal process chamber equipped with a flash lamp annealing system, were designed and introduced. Now the whole system is ready for real fabrication process.
National Institute of Advanced Industrial Science and Technology (AIST) is responsible for development of chemical vapor deposition (CVD) technology for rare-earth and alkali-earth metal oxides which are promising candidates for the second-generation high-k gate dielectrics materials. In FY2009, a CVD system to be employed for reaction-system survey and growth-condition optimization was designed, constructed, and put into operation. This system features a quartz-tube reactor in which a plug-flow condition can be realized for the reaction analyses studies. The CVD reactor is connected to a load-lock chamber which can be expanded to include metal-gate deposition and/or annealing capabilities. Using this CVD system, CeO2 growth by thermal decomposition of Ce precursors were investigated. Auger electron spectroscopy analyses of the obtained films showed Ce and O Auger signals, verifying deposition of pure Ce oxide. Thickness uniformity over a 2 inch wafer was 20% at a growth rate of 2.5 nm/min, which is to be improved in the future studies. Capacitance-voltage measurements showed the dielectric constant of the obtained films is higher than 20. Growth experiments for La2O3 are now in progress.
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