成果報告書詳細
管理番号20100000001156
タイトル*平成21年度中間年報 次世代高効率ネットワークデバイス技術開発(1)
公開日2010/11/10
報告書年度2009 - 2009
委託先名財団法人国際超電導産業技術研究センター
プロジェクト番号P07012
部署名電子・情報技術開発部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等 (1) SFQ回路を用いた光ネットワーク技術開発に用いる超電導回路の開発 SFQリアルタイムオシロスコープの中核部品であるSFQ4ビットADコンバータ(ADC)の高速動作試験を行った結果、図1に示すように最高34GS/sまで動作することが確認された。このサンプリング周波数は中間目標30GS/sを上回る値である。実験に用いたジョセフソン接合(JJ)の臨界電流密度(Jc)は2.5kA/cm2であった。この性能はシミュレーションで予測された値であり、今後Jcの向上により、既存技術を大きく越えると予測されているSFQリアルタイムオシロスコープの性能が実現できる目処が立った。
英文要約Title: Development of Next-generation High-efficiency Network Device Technology (FY2007-FY2009)FY2009 Annual Report
High-speed Analog to Digital Converter (ADC) is a key component of a real-time oscilloscope. We have developed Single-Flux-Quantum (SFQ) ADC with 4-bit accuracy. The SFQ ADC was tested with high-sampling frequency and successfully confirmed its correct operation up to 34 GS/s. This sampling frequency exceeded our interim target. We used Josephson junctions (JJ) with critical current density (Jc) of 2.5 kA/cm2 in the circuit. Because this sampling frequency agrees with simulation results, we can expect to realize an ultimate performance of SFQ real-time oscilloscope which is far exceeding performance of conventional real-time oscilloscopes. The ADC was combined with an error correction circuit which compensated errors caused by gray-zone in ADC comparator threshold characteristics. The combined circuit was fabricated by our Nb 2.5 kA/cm2 process. Error correction operation which selects one of two comparators in the upper bit depending on their lower bit state was carried out and input data were successfully digitized by the circuit. This is the first operation of the ADC with an error correction circuit as far as we know. The SFQ circuit was cooled down to its operation temperature by a cryo-cooler and confirmed its operation. ISTEC and Nagoya University simulated an SFQ frequency divider and shift register circuit with Jc of 40 kA/cm2 in order to explore SFQ possibility. The simulation results predicted that the frequency divider and shift register can be operated up to 500 GHz and 180 GHz, respectively. We also designed and fabricated these circuits. We proposed an optical output scheme from SFQ circuits. In this scheme, outputs voltage from SFQ circuits is amplified by both a superconductive driver and a semiconductor amplifier which is placed at 50 K stage of a cryo-cooler and the amplified voltage rotates optical phase in a LN-modulator. We expect that optical output more than 10 Gbps is possible using the scheme. ISTEC and Yokohama National University investigated driver and receiver circuits for current recycle technology by a three-dimensional inductance simulator and found out that stray inductance caused degradation of their operation margin. A new vertical design for driver and receiver circuits with smaller stray inductance was proposed and confirmed their stable operations. Mounting method of an SFQ Multi Chip Module (MCM) to a cryo-cooler was improved by introducing a package module. This module enable us easier mounting and five times higher heart transfer efficiency from the MCM to the cryo-cooler.
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