成果報告書詳細
管理番号20100000001249
タイトル*平成21年度中間年報 ナノエレクトロニクス半導体新材料・新構造ナノ電子デバイス技術開発 新構造FinFETによるSRAM技術の研究開発
公開日2011/1/8
報告書年度2009 - 2009
委託先名独立行政法人産業技術総合研究所
プロジェクト番号P09002
部署名電子・情報技術開発部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等
(1) 立体構造FinFET 技術の研究開発
これまでに進めているTiN ゲートFinFET 微細加工技術をさらに高度化を推進し、TiN ゲートウェットエッチングを用いた実効ゲート長20nm 級FinFET 作製プロセスを構築した。本プロセスでは、まずはじめに、SOI 基板上にFin チャネルを形成する。ゲート酸化膜成膜後に、20nm 厚のPVD-TiN と100nm 厚のポリSi をゲート材料として堆積する。ドライエッチングによりポリSi ゲートを異方性加工した後、露出したTiN をウェットエッチングにより当方性加工を施す。この際、ゲート側壁においてTiN が当方性加工を受けることになり、図1に示す通り、ポリSi ゲート加工寸法よりも、小さなTiN ゲートが実現可能となる。TiN ゲートのウェット加工には、60°C のAPM(NH4OH:H2O2:H2O =1:2:5)水溶液を用いた。また、図2に示す通り、作製したFinFET の電気的特性を評価した結果、TiN 実効ゲート長が20nm のものにおいて良好なS 係数(80mV/dec.以下)を示すことも確認した。
英文要約Title: Development of Nanoelectronic Device Technology Project, Development of Highly Reliable SRAM Circuits Utilizing Advanced FinFET (FY2009-FY2010) FY2009 Annual Report
The nanoscale TiN wet etching and its application for FinFET fabrication have been systematically investigated. It was found that the TiN side-etching can be controlled to be half of TiN thickness with precise time control. By using the developed nanoscale TiN wet etching technique, 20-nm physical gate length FinFETs have successfully been fabricated. FinFET performance variability was comprehensively investigated for undoped/doped channels with various gate materials. By evaluating the influence of channel doping, fluctuation of gate length and that of fin thickness, it was found that gate workfunction variation (WFV) is the dominant source of Vth variation for the undoped FinFET and that the WFV increases with scaling of gate area. The low-energy tilted ion implantation (I/I) for FinFET source-drain extension doping has been investigated thoroughly by fabricating a series of n+-poly-Si gate n-channel FinFETs with different I/I conditions. It was experimentally confirmed that the best extension I/I condition is Dose = 4x14 cm-2 & θ = 60o. With further increasing Dose, the device performance deteriorated due to the incomplete re-crystallization of amorphous regions in the fin extensions. In the case of θ = 0o, the marked increment and fluctuations in parasitic resistance were observed owing to the implant atoms scattering out randomly from each fin extension. As a gate insulator, HfO2-based high-k dielectric insulator was introduced into FinFET SRAM using ALD. It was confirmed that the EOT and dielectric constant are 2.1nm and 1.9, respectively. Variability of the TiN FinFET SRAM cell performance was comprehensively studied. It was found that the static noise margin (SNM) variation of the SRAM cell is due to the Vth variation of FinFETs caused by the work function variation (WFV) of the TiN metal-gate. It was experimentally demonstrated that the Flex-Pass-Gate-SRAM using Vth-controllable independent-double-gate FinFET technology successfully compensates not only the random variation but also the systematic variation problems. As a result, Flex-Pass-Gate-SRAM technology enabled 0.5 V operation with a high cell stability. Stand-by leakage current for the 20-nm-node Flex-Pass-Gate SRAM array was compared to the conventional bulk CMOS SRAM by using TCAD simulation. Taking the performance variation such as dimension variation, random dopant fluctuation and WFV into account, the stand-by leakage current for the Flex-Pass-Gate SRAM array was expected to be 1/30 as compared to that for the conventional bulk SRAM array.
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