成果報告書詳細
管理番号20100000001254
タイトル*平成21年度中間年報 ナノエレクトロニクス半導体新材料・新構造ナノ電子デバイス技術開発 シリコンプラットフォーム上3ー5族半導体チャネルトランジスタ技術の研究開発
公開日2011/1/8
報告書年度2009 - 2009
委託先名国立大学法人東京大学 独立行政法人物質・材料研究機構 独立行政法人産業技術総合研究所
プロジェクト番号
部署名電子・情報技術開発部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等 (1)研究開発の内容
電子の有効質量が小さく移動度が大きいIII-V族半導体を用いたMISFETは、hp22nm以細のCMOSにおける性能向上や低消費電力化を可能にするデバイスとして期待されている。このデバイスが適用される技術世代においては、高い電流駆動力を持ち、かつ、短チャネル効果抑制にも優れたMISFETを、絶縁膜の上に薄膜III-V化合物半導体を形成したIII-V-On-Insulator (III-V-OI)構造を用いてSiプラットホーム上にて実現することが求められる。
本研究は、Si基板上更にその上の絶縁膜上に形成したIII-V族半導体をチャネルとするMISFETを開発するために、最適素子構造・材料の明確化を進め、本デバイスの当該世代CMOSへの適用性を明らかにすると共に、集積化可能性を検証することを最終目標として研究開発を進めている。
英文要約Title: Development of Nanoelectronic Device Technology, Development of Transistor Technology Incorporating III-V Semiconductor Channels on Si Platform (FY2009-FY2010) FY2009 Annual Report
In this study, we are developing MISFETs using III-V channels on Si substrates or insulating layers on Si. In order to realize this device, we have performed the following researches. As for the epitaxial growth of III-V channels on Si, we have proposed a multi-step growth method, where the amount of Ga source supply is varied along the time sequence of the epitaxial growth. As a result, the improvements of the uniformity of the morphology, the lateral growth properties and the surface flatness and the realization of dislocation-free films without any twins have been obtained. Also, we have successfully fabricated 7-nm-thick InGaAs-OI structures by thinning InGaAs layers with ECR SiO2 buried oxides, bonded to Si substrates. We have realized III-V-OI structures with superior MOS interfaces by employing surface activation method utilizing Ar beam irradiation or direct bonding method. We have clarified that ECR plasma nitridation of InGaAs surfaces and successive annealing can realize ECR sputtered SiO2/InGaAs MOS structures with superior interface properties such as low interface state density of the lower half of 1E11 cm-2eV-1 order and small hysteresis lower than 50 mV. We have found through the correlation between electrical properties and XPS spectra that the suppression of As oxides is effective in improving the MIS interface properties and that the superior interface s by the nitridation/annealing process are attributable to the formation of Ga-N bonds. To realize high-quality interface between high-k dielectrics and III-V compound semiconductors, we systematically controlled the structure and composition of the interface at an atomic level: Ga atoms at the HfO2/InGaAs interface are substituted by Al and In atoms. In addition, UHV chambers equipped with the atomic hydrogen source has been constructed for the formation of high quality HfO2/InGaAs interfaces. Basic formation processes for the gate stack consisting of InGaAs and ALD-Al2O3 have been developed by clarifying the effects of thermal treatments as well as by controlling the interface/surface properties by using (NH4)2S and plasma treatments. Concerning the metal source/drain MOSFET technology, we have found through the experimental examination of the Schottky barrier height that AuGe and Ni are promising materials for InP nMOSFETs. Based on this finding, we have demonstrated the MOSFET operation of InP nMOSFETs with AuGe source/drain. The III-V MISFET fabrication process has been established using the InGaAs(100) channel, and channel mobility exceeding the Si universal mobility has been verified. Furthermore, it has been found that the mobility for the InGaAs(111)A channel is higher than the (100) channel, showing more than twice improvements with respect to Si. Top-gate MISFETs built on the III-V-OI structure have also been demonstrated. Source-drain formation by ion implantation has been optimized, and the issues for the parasitic resistance reduction have been identified.
ダウンロード成果報告書データベース(ユーザ登録必須)から、ダウンロードしてください。

▲トップに戻る