成果報告書詳細
管理番号20110000000523
タイトル*平成22年度中間年報 省エネルギー革新技術開発事業 先導研究 第2世代超薄膜ゲート絶縁膜材料の研究開発
公開日2011/5/10
報告書年度2010 - 2010
委託先名国立大学法人東京工業大学 独立行政法人産業技術総合研究所
プロジェクト番号P09015
部署名エネルギー対策推進部
和文要約和文要約等以下本編抜粋:1.研究開発の内容及び成果等
(1)研究開発の内容
温室効果ガスの排出量の大幅な削減は地球環境の観点から必ず実現しなければならない事であり、国の公約にもなっている。そのためには一次エナルギーから動力・熱・光・電気など二次エネルギーへの交換効率を高めるとともに、製造、交通・運輸、情報・通信、家庭、オフィスなどあらゆるシステムムの動作効率を高めていくことも非常に重要である。システムの動作効率を高めるためには、システムを精密に制御する必要があり、集積回路を主な部品とする制御機器類が多く必要となる。また、最近のITの急激な普及とそれに伴う情報通信量の爆発的とも言える増大によってデータセンター、ルータ、PC、携帯端末など集積回路を主な部品とする情報機器類も大幅に増えてきているため、その集積回路自身の消費エネルギーを削減することが求められるようになって来ている。集積回路に搭載されるMOSFETの数は今後も増加し続ける見通しであり、MOSFET自身の低消費電力化が集積回路全体の低消費電力化にきわめて重要である。微細化の極限を追求して電源の低電圧化を実現することが半導体省エネ化のための最も有効な手段であるが、MOSFETのゲート絶縁膜の薄膜化が微細化を阻む最大の要因となっている。
英文要約Title: Leading Research Project for Development of Innovative Energy Conservation Technologies, Development of the Second-Generation Ultrathin Gate-Dielectrics Materials (FY2009-FY2011) FY2010 Annual Report
Reducing the power consumption of large-scale integrated circuits (LSIs) is critically important in order to suppress the emission of the greenhouse gases in various systems. Scaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) devices has been most effective for lowering the operation voltage and thereby reducing the power consumption of the LSIs. This study aims to develop ultrathin gate-dielectric materials that enable high drain current and carrier mobility in the direct-contact high-k/Si gate stack with equivalent oxide thickness (EOT) of 0.5nm. The final goal is to prove that the second-generation high-k gate stack incorporating the direct-contact interfaces is a feasible technology and is worth further investigation toward commercialization.
In order to realize second-generation high-k gate stack technology with EOT of 0.5nm, key technologies on the controlling of the interface between high-k and silicon direct-contact and also the interface between gate metal and high-k were studied. Direct contact of high-k gate dielectric and silicon substrate with EOT less than 0.5nm was realized by using La2O3 as the high-k and TiN/W stack as the gate metal. Process technologies for improving the interface properties of high-k/ silicon and also gate metal/high-k were studied by optimizing process conditions such as deposition conditions, W layer thicknesses, annealing conditions and also by developing new structures such as inserting Si layer at the interface between gate metal and high-k. Applying those developed technologies, MOSFETs with EOT of 0.5nm were successfully fabricated. Studies focused on the technology for overcome the mobility degradation in MOSFETs with EOT of 0.5nm and beyond are now in progress.
As for the exploration and optimization of CVD for the high-k dielectrics formation, the film growth processes of La2O3, CeO2, MgO, and SrO were investigated using the various metal sources (cyclopentadienyls, alchoxides, and amidinates) and H2O. Deposited films were evaluated in terms of the thickness uniformity, refractive index, surface roughness, among others. The growth processes were also examined to clarify whether the self-limiting ALD mode is possible. It was found that the La2O3 films prepared in the ALD mode using the La cyclopentadienyl source met all the specifications. Thermal decomposition of the Ce alchoxide also formed quality CeO2 films. CVD/ALD processes for MgO and SrO were established. In order to evaluate the electrical properties of these high-k films without the interfering effects of H2O and CO2 absorption, the CVD apparatus was modified to include a sputtering chamber for in-situ metallization. As for the reduction of the impurities in the high-k films, it was demonstrated that annealing the La2O3 films at 500 degree C effectively reduced the carbon concentration in the films down to less than 1 atomic-%.
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