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成果報告書詳細
管理番号20180000000162
タイトル*平成29年度中間年報 IoT推進のための横断技術開発プロジェクト 組合せ最適化処理に向けた革新的アニーリングマシンの研究開発
公開日2018/6/2
報告書年度2017 - 2017
委託先名株式会社日立製作所 国立研究開発法人産業技術総合研究所 国立研究開発法人理化学研究所 大学共同利用機関法人情報・システム研究機構 学校法人早稲田大学
プロジェクト番号P16007
部署名IoT推進部
和文要約
英文要約Title: Project to develop cross-sectoral technologies for IoT promotion, Research and Development of Innovative Annealing Machine for Combinatorial Optimization Processing (FY2016-FY2018)
FY2017 Annual Report

Hitachi fabricated a CMOS annealing chip to verify the multiple-chip operation of CMOS annealing machine. In the chip, King's graph for Ising model topology is used and 30kbit spins is installed in area of 4.3x5.5 mm^2. The bit number of interaction coefficient is set to 3bits. The inter-chip interface with LVDS is used and the performance using 2-chip connection will be evaluated in 2018.

AIST developed device structures and fabrication processes for qubit chip consisting of qubits and couplers and active interposer chip including readout and control circuits. AIST also developed one chip device structure and fabrication process for test circuits of ASAC three-bit factoring machine and its elemental circuits. The one chip circuits were designed as a photomask and started its fabrication. Flip-chip fabrication process and test circuits in which about 30,000 bumps were serially connected were developed. The minimum bump size of 10 um diameter was successfully fabricated. The flip-chipped qubits were confirmed cooling to low enough by thermal analysis.

The detailed architecture of the superconducting quantum annealing system that enables a full coupling was developed by RIKEN. The number of maximum spins that can be integrated into the system is estimated to be about one hundred. RIKEN's another research goal is to develop optimization-problem solvers utilizing parametric oscillation in superconducting circuits. In this year, RIKEN have designed and fabricated impedance-engineered Josephson parametric amplifiers (IMPA), which utilize non-linearity of superconducting tunnel junctions (Josephson junctions) for parametric amplification. The device is under testing in our dilution refrigerator system. Our theoretical analysis has demonstrated broadband gain characteristics of our amplifier design.

CMOS machine in our proposal deals with only a special kind of graphs. Specifically, it only handles a ``king graph'', which consists of 4 layers of a grid graph. NII has implemented a fast and scalable Simulated Annealing algorithm for the max-cut problem on this king graph of order up to 4 million vertices. It turns out that we can obtain a reasonably good solution (which is comparable to a solution of the SDP algorithm for the max-cut problem) in around 20 seconds.

Waseda Univ. developed an embedding method of combinatorial optimization problems to CMOS annealing machines. The performance of CMOS annealing machine for graph partitioning problem and rectangle packing problem is confirmed. The effect of new type of fluctuation which can be introduced in the quantum annealing machine is also studied. By adding the new kind of fluctuation, the performance of quantum annealing machine increases. A part of the study was done in collaboration with AIST group.
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