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成果報告書詳細
管理番号20180000000179
タイトル*平成29年度中間年報 IoT 推進のための横断技術開発プロジェクト 超低消費電力データ収集システムの研究開発5(国立大学法人神戸大学)
公開日2018/6/2
報告書年度2017 - 2017
委託先名国立大学法人神戸大学
プロジェクト番号P16007
部署名IoT推進部
和文要約
英文要約Title: Project to Develop Cross-Sectoral Technologies for IoT Promotion / Development of Ultra Low Power Data Collection Systems (FY2016-FY2018) FY2017 Annual Report

This research consists of two VLSI design technology developments. One is the development of a low-power digital architecture and the other is the development of high efficiency power circuits.
For the low-power digital architecture, we developed vertical integration control techniques between base-station (BS) and sensor nodes in order to realize both a traffic reduction and a power reduction in the network including cloud. In order to minimize data transmission power by vertical cooperative control, data compression by compression sensing and implementation of feature amount extraction method by multiple frequency analysis were performed. Also a frequency analysis method based on the AR model was adopted as a method suitable for reducing the communication amount between the IoT node and the BS. In order to realize the horizontal cooperative control, we evaluated the wireless communication power using the commercial BLE wireless module. Also, we developed a measurement circuit and signal processing algorithm aiming at improving availability at low active ratio. By using the proposed technique, it is seen that we may be able to achieve 1 / 10th power consumption compared to the conventional technology in healthcare application using photoelectric pulse wave. For the development of integrated SoC (LSI-A), we evaluated the prototype chip (TEG) and a leaf prototype system (PTS) for emulation equipped with various TEGs. The evaluation result will be reflected in the integrated LSI-A external specification.
For the study of high efficiency power circuits, a high-efficiency buck-boost voltage converter, power management techniques, and power conversion systems are developed through the fabrication and measurement of 1st and 2nd prototype chips.
By the circuit simulation using TSMC 65nm LP process parameters, it was confirmed that the converter generates a six times higher voltage from the output voltage of the harvester (ー0.5 V). We also found that the output voltage decreases as the load current increases. The maximum power conversion efficiency was 79%. So it was seen that the circuit can achieve high efficiency. However, we found that the power conversion efficiency degrades after performing the post-layout simulations. This was because of the parasitic resistance and capacitance of the circuit. We have to design our circuit with less parasitic resistance and capacitance. We fabricated a test chip of the circuit using TSMC 65-nm process. In the 1st prototype chip, we were not able to achieve sufficient trimming accuracy due to the trouble in the trimming switch. In the 2nd test chip, we achieved comparable performance with the simulation by modifying the trimming switches.
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