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成果報告書詳細
管理番号20180000000184
タイトル*平成29年度中間年報 IoT推進のための横断技術開発プロジェクト 超低消費電力データ収集システムの研究開発9(国立大学法人東京大学)
公開日2018/6/2
報告書年度2017 - 2017
委託先名国立大学法人東京大学
プロジェクト番号P16007
部署名IoT推進部
和文要約
英文要約Title: Project to develop cross-sectoral technologies for IoT promotion
/Development of Ultra Low Power Data Collection Systems (FY2016-2018) FY2017 Annual Report

1) Quick Start PLL
This research proposed a quick start PLL for ultra low power IoT devices.
We utilize our Pulse Width Controlled PLL, PWPLL, that has possibility to reduce power consumption by lowering the power supply voltage. We can further reduce the power consumption of the system by shortening the lock time, assuming a system with short ON time while most of time are in sleep mode.
In an architecture that the operating frequency is the same at every ON time, the internal conditions of a PLL including the thermometer code and counter value are also the same at every wake-up. Thus, the value of the thermometer code and the counter value at the locked state are stored in an outside memory at the end of the operation before going into the sleep mode, and at the next wake-up time, the PLL reads and restores the value as the initial condition, so that the PLL lock time can be shortened. In order to realize the system, our quick start PLL uses DFFs with the thermometer code generation block and the counter for memorize its oscillation frequency, in addition, the PLL utilize TDC and DTC to memorize the phase information as well.
We implemented this proposed circuit with TSMC 65nm process. Measurement results confirm the operation that the lock time is as short as 50ns (1 reference CLK period) with the power consumption of 95uW under the layout area is 20um x 150um.

2) Quick Start CDR
In this research, a new circuit structure of small area CDR circuits using Self-Tunable Digitally Controlled Delay Line (ST-DCDL) is developed, and it realizes low power consumption. The CDR circuit can start up with a preamble of only 4 bits from the stand-by state. It is enabled by a Time to Digital Converter that immediately acquires the period of the input signal, working with a DCDL that makes the internal oscillation frequency instantaneously follow the input signal period.
The Dely Tunable Buffer adjust the delay by digitally changing the current value by the external code. The delay is designed to change linearly by the corresponding digital code. At the same time, the Vernier TDC is designed with its resolution is 1 LSB of the DTB.
We implemented the proposed CDR circuit with TSMC 65nm process. Measurement results confirm that the CDR correctly recovers the clock and data signals only with 4-bit preamble for 160Mbps random data input with the power consumption of 300uW at 0.6V supply. The layout area is 98um x 157um.
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