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成果報告書詳細
管理番号20190000000371
タイトル*平成30年度中間年報 高効率・高速処理を可能とするAIチップ・次世代コンピューティングの技術開発/革新的AIエッジコンピューティング技術の開発/スケーラブルなエッジHPCを実現するOS統合型プラットフォームの研究開発
公開日2019/5/28
報告書年度2018 - 2018
委託先名イーソル株式会社 国立大学法人名古屋大学
プロジェクト番号P16007
部署名IoT推進部
和文要約
英文要約Title:Project for Innovative AI Chips and Next-Generation Computing Technology Development/Development of Innovative AI Edge Computing Technologies/OS-integrated platform for scalable HPC (FY2018-FY2020) FY2018 Annual Report

The goal of this project is to develop an OS-integrated software platform including software mapping tools for scalable HPC. It consists of five research topics; Distributed MK, Integrated SOC for distributed MK, Hybrid-scheduling/Load-balancing algorithm, Software Mapping Tools, and Hardware-description model for heterogenous multi-manycore. This summary briefly describes the current status of the research.

1. Distributed MK
A mechanism for supporting distributed shared memory architecture, message queue management for heterogeneous processors, inter-process messaging for POSIX profile, a mechanism for temporal partitioning, among others, have been performed. The goal of this research topic for the year has been achieved, by successfully demonstrating running eMCOS over two different processor architectures, namely NXP S32V and KALRAY MPPA, connected via its message passing mechanism.

2. Integrated SOC for distributed MK
A messaging passing transformer for heterogenous-chip communication, design, and implementation of various service modules based on the distributed MK message passing, and others have been performed. The goal of this research topic for the year has been achieved, as it is the same as the one for the previous research topic.

3. Hybrid-scheduling/Load-balancing algorithm
Communication profiling and the load-balancing algorithm based on the profile has been prototyped on KALRAY MPPA, which also archives the goal of this research topic for the year. A preliminary evaluation of the algorithm against the current algorithm has been performed. The result shows the new algorithm is 50% superior in terms of the resulting performance of the application.

4. Software Mapping Tools
We proposed a software mapping algorithm for single-ISA heterogeneous processors and started to research on an algorithm for general heterogeneous processors. A translator from C/C++ function call graphs into our internal data structure BLXML (Block-Level structure XML) was developed, so that our task assignment tool MBP can assign C/C++ functions to processor cores. We selected the AMALTHEA component model as our system description and started to describe a system into the model. Other activities are also performed.

5. Hardware-description model for heterogenous multi-manycore
The Multicore Association’s SHIM WG, which is chaired by eSOL, has developed and published a new version of SHIM in January. This new version of SHIM supports more precise performance estimation of target software, which achieves the goal of this research topic for the year. A new IEEE standard, a new PAR P2804 has been created and submitted to IEEE. It was approved by IEEE Standard Board in February. The chair of new WG, C/DA/SHIM, has been assigned to Masaki Gondo of eSOL.
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