本文へジャンプ

成果報告書詳細
管理番号20190000000388
タイトル*平成30年度中間年報 高効率・高速処理を可能とするAIチップ・次世代コンピューティングの技術開発/革新的AIエッジコンピューティング技術の開発/再帰再構成型ニューロモルフィックアクセラレータの研究開発
公開日2019/6/22
報告書年度2018 - 2018
委託先名国立大学法人熊本大学
プロジェクト番号P16007
部署名IoT推進部
和文要約
英文要約Title: Project for Innovative AI Chips and Next-Generation Computing Technology Development/Development of Innovative AI Edge Computing Technologies/A Study of Recurrent Reconfigurable Neuromorphic Accelerator (FY2018-FY2019) FY2018 Annual Report

We explorer deep neural network (DNN) specific hardware (HW) architectures to achieve high-performance and low-power for deep learning applications. We plan to complete the base architecture research in April and determine the chip specification in June 2019, then design and evaluate the proposed LSI with TSMC 40nm. Our research status is summarized in the following five subjects.
(1) DNN-specific HW architecture exploration
We are exploring DNN architecture on PE cluster structure, routing resources. A PE cluster is designed to process a neuron of a feature map with a bit-serial computing unit. We found it is sufficient to use the nearest neighbor connection for DNN feature map processing, which reduces hardware resources and improves DNN kernel density than a conventional FPGA routing. We will determine the circuit design in the next April.
(2) Research of PE functions
We have designed gray code adder and multiplier circuits that can perform the calculation from MSB, which allow neglecting calculations of low-order bits if high-order bits can meet an application's accuracy requirement. We found that for 8-bit addition without cutting low-order bits, the proposed gray code adder with 3-bit registers can achieve an average calculation accuracy of 98.56%. We will continue to research on stream calculation approach.
(3) CAD tool development
In the front-end, we leverage ONNX runtime, which can convert DNN models of various design frameworks to the standard ONNX format. The back-end flow consists of several novel tools, which convert ONNX model to files for configuring the proposed LSI. During this term, we have finished the conversion program for generating Re2NA weight bitstream. We will finish the placement, routing and bitstream generation tools in June 2019.
(4) DNN architecture model evaluation
We have investigated the influence on the accuracy of pruning unnecessary weights and unimportant neurons. We found the DNN quantization technique used in SW frameworks changes accuracy for different layers, which is not suitable for HW implementation. In addition, current DNN frameworks cannot correctly measure the error rate reduction with a specified calculation accuracy. Therefore, we have modified the current DNN framework and performed the above investigations.
(5) LSI chip design
We determined to develop our LSI base on a RISC-V architecture processor called Freedom. We expanded the interrupt module for the proposed AI chip and verified its functions by making a prototype on an FPGA. We determined to use AXI bus as the connection interface for AI chip. We also proposed RISC-V oriented development environment for the controlling program of the AI chip.
ダウンロード成果報告書データベース(ユーザ登録必須)から、ダウンロードしてください。

▲トップに戻る