本文へジャンプ

成果報告書詳細
管理番号20190000000407
タイトル*平成30年度中間年報 高効率・高速処理を可能とするAIチップ・次世代コンピューティングの技術開発/次世代コンピューティング技術の開発/2028年に性能100倍を達成する汎用性の高い高性能計算機アーキテクチャとシステムソフトウェアの技術の探索
公開日2019/6/22
報告書年度2018 - 2018
委託先名国立研究開発法人理化学研究所 国立大学法人東京工業大学 国立大学法人東京大学
プロジェクト番号P16007
部署名IoT推進部
和文要約
英文要約Title:Project for Innovative AI Chips and Next-Generation Computing Technology Development/Development of Next-Generation Computing Technologies/Exploring technologies of general-purpose and high-performance computing architectures and their system software which are expected to achieve relatively x100 times higher performance in 2028 (FY2018-FY2020) FY2018 Annual Report

The objective of this project is to explore promising technologies to achieve 100 times higher performance around 2028 in the so-called Post-Moore era. We carefully select proxy applications reflecting an enough coverage of the real-world application workloads to evaluate candidate techniques by comparing with current ones which are designed for high-end general-purpose processors and systems. We tackle the following sub-themes:

1.1 Performance modeling and simulation environment (RIKEN)
To explore promising computer architectures, we need to be able to evaluate and analyze a wide range of architecture candidates varying their configurations. The objectives of this sub-theme are: 1) collecting a set of applications for architecture evaluation and analyzing their characteristics; 2) establishing performance models and simulation environments. In this fiscal year, we first examined several benchmarks from the categories of HPC, Big Data, and AI areas. We investigated PARADISE, a computer architecture simulation tool set for the Post-Moore era. We selected 21 Exa-scale benchmarks, and conducted detailed analysis. The results suggest that practically most of the HPC applications are memory bound, and performance can be improved not by increasing ALUs, but memory bandwidth, as we had originally conjectured.

1.2 Non-von-Neumann computing mechanisms and programming model (RIKEN)
We explore new non-von-Neumann architectures including coarse-grain reconfigurable ones (CGRAs) and their programming methodologies in order to discover processor organization promising in the forthcoming Post-Moore era. In this fiscal year, we preliminary investigated design space of the architectures by surveying CGRAs and future processor architectures. We considered parameters required to define our target design space for architecture exploration.

2 System-software technology for memory-architecture innovation (Titech)
Our target is to harness memory hierarchy efficiently, which will be deeper and more complex from the aspect of system software. In this fiscal year, we worked on: (a) modelling heterogeneous memory hierarchy, where we started evaluation of future memory hierarchy, and (b) Data scheduling technology for deeper memory hierarchy, where we surveyed system software for memory hierarchy including GASNet and UPC++. We have implemented a prototype library of automatic memory movement and evaluated it with simple stencil computations.

3 High-performance programming models and implementation techniques (The University of Tokyo)
We explore technologies to drive performance of future architectures, such as high bandwidth memory and high bandwidth optical networks, investigate programming models and implementation techniques that take advantage of them, and assess performance of representative applications. In this fiscal year, we worked on performance analysis tools and modeling, scalable distributed shared memory and locality-aware dynamic load balancing algorithm.
ダウンロード成果報告書データベース(ユーザ登録必須)から、ダウンロードしてください。

▲トップに戻る